Re: [PATCH 1/2] arm64: kvm: Save/restore MTE registers

From: kernel test robot
Date: Mon Jul 13 2020 - 20:00:02 EST

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In reply to: Steven Price: "[PATCH 1/2] arm64: kvm: Save/restore MTE registers"
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Hi Steven,

I love your patch! Yet something to improve:

[auto build test ERROR on v5.8-rc5]
[cannot apply to kvmarm/next arm64/for-next/core arm-perf/for-next/perf next-20200713]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Steven-Price/MTE-support-for-KVM-guest/20200713-180255
base: 11ba468877bb23f28956a35e896356252d63c983
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All errors (new ones prefixed by >>):

arch/arm64/kernel/relocate_kernel.S: Assembler messages:
>> arch/arm64/kernel/relocate_kernel.S:44: Error: non-constant expression in ".if" statement
>> arch/arm64/kernel/relocate_kernel.S:44: Error: non-constant expression in ".if" statement
>> arch/arm64/kernel/relocate_kernel.S:44: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/relocate_kernel.S:44: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/relocate_kernel.S:44: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/relocate_kernel.S:44: Error: invalid operands (*ABS* and *UND* sections) for `|'
--
arch/arm64/kernel/cpu-reset.S: Assembler messages:
>> arch/arm64/kernel/cpu-reset.S:35: Error: non-constant expression in ".if" statement
>> arch/arm64/kernel/cpu-reset.S:35: Error: non-constant expression in ".if" statement
>> arch/arm64/kernel/cpu-reset.S:35: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/cpu-reset.S:35: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/cpu-reset.S:35: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kernel/cpu-reset.S:35: Error: invalid operands (*ABS* and *UND* sections) for `|'
--
arch/arm64/kvm/hyp-init.S: Assembler messages:
>> arch/arm64/kvm/hyp-init.S:105: Error: non-constant expression in ".if" statement
>> arch/arm64/kvm/hyp-init.S:105: Error: non-constant expression in ".if" statement
arch/arm64/kvm/hyp-init.S:149: Error: non-constant expression in ".if" statement
arch/arm64/kvm/hyp-init.S:149: Error: non-constant expression in ".if" statement
>> arch/arm64/kvm/hyp-init.S:105: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kvm/hyp-init.S:105: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kvm/hyp-init.S:105: Error: invalid operands (*ABS* and *UND* sections) for `|'
>> arch/arm64/kvm/hyp-init.S:105: Error: invalid operands (*ABS* and *UND* sections) for `|'
arch/arm64/kvm/hyp-init.S:149: Error: invalid operands (*ABS* and *UND* sections) for `|'
arch/arm64/kvm/hyp-init.S:149: Error: invalid operands (*ABS* and *UND* sections) for `|'
arch/arm64/kvm/hyp-init.S:149: Error: invalid operands (*ABS* and *UND* sections) for `|'
arch/arm64/kvm/hyp-init.S:149: Error: invalid operands (*ABS* and *UND* sections) for `|'
--
In file included from arch/arm64/kvm/sys_regs.c:32:
>> arch/arm64/kvm/sys_regs.c:1524:13: error: 'SYS_RGSR_EL1' undeclared here (not in a function); did you mean 'SYS_DISR_EL1'?
1524 | { SYS_DESC(SYS_RGSR_EL1), trap_raz_wi, reset_unknown, RGSR_EL1 },
| ^~~~~~~~~~~~
arch/arm64/kvm/sys_regs.h:156:25: note: in definition of macro 'Op0'
156 | #define Op0(_x) .Op0 = _x
| ^~
arch/arm64/kvm/sys_regs.h:164:6: note: in expansion of macro 'sys_reg_Op0'
164 | Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
| ^~~~~~~~~~~
arch/arm64/kvm/sys_regs.c:1524:4: note: in expansion of macro 'SYS_DESC'
1524 | { SYS_DESC(SYS_RGSR_EL1), trap_raz_wi, reset_unknown, RGSR_EL1 },
| ^~~~~~~~
>> arch/arm64/kvm/sys_regs.c:1525:13: error: 'SYS_GCR_EL1' undeclared here (not in a function); did you mean 'SYS_TCR_EL1'?
1525 | { SYS_DESC(SYS_GCR_EL1), trap_raz_wi, reset_unknown, GCR_EL1 },
| ^~~~~~~~~~~
arch/arm64/kvm/sys_regs.h:156:25: note: in definition of macro 'Op0'
156 | #define Op0(_x) .Op0 = _x
| ^~
arch/arm64/kvm/sys_regs.h:164:6: note: in expansion of macro 'sys_reg_Op0'
164 | Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
| ^~~~~~~~~~~
arch/arm64/kvm/sys_regs.c:1525:4: note: in expansion of macro 'SYS_DESC'
1525 | { SYS_DESC(SYS_GCR_EL1), trap_raz_wi, reset_unknown, GCR_EL1 },
| ^~~~~~~~
>> arch/arm64/kvm/sys_regs.c:1550:13: error: 'SYS_TFSR_EL1' undeclared here (not in a function); did you mean 'SYS_DISR_EL1'?
1550 | { SYS_DESC(SYS_TFSR_EL1), trap_raz_wi, reset_unknown, TFSR_EL1 },
| ^~~~~~~~~~~~
arch/arm64/kvm/sys_regs.h:156:25: note: in definition of macro 'Op0'
156 | #define Op0(_x) .Op0 = _x
| ^~
arch/arm64/kvm/sys_regs.h:164:6: note: in expansion of macro 'sys_reg_Op0'
164 | Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
| ^~~~~~~~~~~
arch/arm64/kvm/sys_regs.c:1550:4: note: in expansion of macro 'SYS_DESC'
1550 | { SYS_DESC(SYS_TFSR_EL1), trap_raz_wi, reset_unknown, TFSR_EL1 },
| ^~~~~~~~
>> arch/arm64/kvm/sys_regs.c:1551:13: error: 'SYS_TFSRE0_EL1' undeclared here (not in a function); did you mean 'SYS_AFSR0_EL1'?
1551 | { SYS_DESC(SYS_TFSRE0_EL1), trap_raz_wi, reset_unknown, TFSRE0_EL1 },
| ^~~~~~~~~~~~~~
arch/arm64/kvm/sys_regs.h:156:25: note: in definition of macro 'Op0'
156 | #define Op0(_x) .Op0 = _x
| ^~
arch/arm64/kvm/sys_regs.h:164:6: note: in expansion of macro 'sys_reg_Op0'
164 | Op0(sys_reg_Op0(reg)), Op1(sys_reg_Op1(reg)), \
| ^~~~~~~~~~~
arch/arm64/kvm/sys_regs.c:1551:4: note: in expansion of macro 'SYS_DESC'
1551 | { SYS_DESC(SYS_TFSRE0_EL1), trap_raz_wi, reset_unknown, TFSRE0_EL1 },
| ^~~~~~~~
--
arch/arm64/kvm/hyp/sysreg-sr.c: In function '__sysreg_save_common_state':
>> arch/arm64/kvm/hyp/sysreg-sr.c:30:6: error: implicit declaration of function 'system_supports_mte'; did you mean 'system_supports_bti'? [-Werror=implicit-function-declaration]
30 | if (system_supports_mte()) {
| ^~~~~~~~~~~~~~~~~~~
| system_supports_bti
cc1: some warnings being treated as errors

vim +1524 arch/arm64/kvm/sys_regs.c

1391
1392 /*
1393 * Architected system registers.
1394 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1395 *
1396 * Debug handling: We do trap most, if not all debug related system
1397 * registers. The implementation is good enough to ensure that a guest
1398 * can use these with minimal performance degradation. The drawback is
1399 * that we don't implement any of the external debug, none of the
1400 * OSlock protocol. This should be revisited if we ever encounter a
1401 * more demanding guest...
1402 */
1403 static const struct sys_reg_desc sys_reg_descs[] = {
1404 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1405 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1406 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1407
1408 DBG_BCR_BVR_WCR_WVR_EL1(0),
1409 DBG_BCR_BVR_WCR_WVR_EL1(1),
1410 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1411 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1412 DBG_BCR_BVR_WCR_WVR_EL1(2),
1413 DBG_BCR_BVR_WCR_WVR_EL1(3),
1414 DBG_BCR_BVR_WCR_WVR_EL1(4),
1415 DBG_BCR_BVR_WCR_WVR_EL1(5),
1416 DBG_BCR_BVR_WCR_WVR_EL1(6),
1417 DBG_BCR_BVR_WCR_WVR_EL1(7),
1418 DBG_BCR_BVR_WCR_WVR_EL1(8),
1419 DBG_BCR_BVR_WCR_WVR_EL1(9),
1420 DBG_BCR_BVR_WCR_WVR_EL1(10),
1421 DBG_BCR_BVR_WCR_WVR_EL1(11),
1422 DBG_BCR_BVR_WCR_WVR_EL1(12),
1423 DBG_BCR_BVR_WCR_WVR_EL1(13),
1424 DBG_BCR_BVR_WCR_WVR_EL1(14),
1425 DBG_BCR_BVR_WCR_WVR_EL1(15),
1426
1427 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1428 { SYS_DESC(SYS_OSLAR_EL1), trap_raz_wi },
1429 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1 },
1430 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1431 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1432 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1433 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1434 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1435
1436 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1437 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1438 // DBGDTR[TR]X_EL0 share the same encoding
1439 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1440
1441 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1442
1443 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1444
1445 /*
1446 * ID regs: all ID_SANITISED() entries here must have corresponding
1447 * entries in arm64_ftr_regs[].
1448 */
1449
1450 /* AArch64 mappings of the AArch32 ID registers */
1451 /* CRm=1 */
1452 ID_SANITISED(ID_PFR0_EL1),
1453 ID_SANITISED(ID_PFR1_EL1),
1454 ID_SANITISED(ID_DFR0_EL1),
1455 ID_HIDDEN(ID_AFR0_EL1),
1456 ID_SANITISED(ID_MMFR0_EL1),
1457 ID_SANITISED(ID_MMFR1_EL1),
1458 ID_SANITISED(ID_MMFR2_EL1),
1459 ID_SANITISED(ID_MMFR3_EL1),
1460
1461 /* CRm=2 */
1462 ID_SANITISED(ID_ISAR0_EL1),
1463 ID_SANITISED(ID_ISAR1_EL1),
1464 ID_SANITISED(ID_ISAR2_EL1),
1465 ID_SANITISED(ID_ISAR3_EL1),
1466 ID_SANITISED(ID_ISAR4_EL1),
1467 ID_SANITISED(ID_ISAR5_EL1),
1468 ID_SANITISED(ID_MMFR4_EL1),
1469 ID_SANITISED(ID_ISAR6_EL1),
1470
1471 /* CRm=3 */
1472 ID_SANITISED(MVFR0_EL1),
1473 ID_SANITISED(MVFR1_EL1),
1474 ID_SANITISED(MVFR2_EL1),
1475 ID_UNALLOCATED(3,3),
1476 ID_SANITISED(ID_PFR2_EL1),
1477 ID_HIDDEN(ID_DFR1_EL1),
1478 ID_SANITISED(ID_MMFR5_EL1),
1479 ID_UNALLOCATED(3,7),
1480
1481 /* AArch64 ID registers */
1482 /* CRm=4 */
1483 ID_SANITISED(ID_AA64PFR0_EL1),
1484 ID_SANITISED(ID_AA64PFR1_EL1),
1485 ID_UNALLOCATED(4,2),
1486 ID_UNALLOCATED(4,3),
1487 { SYS_DESC(SYS_ID_AA64ZFR0_EL1), access_id_aa64zfr0_el1, .get_user = get_id_aa64zfr0_el1, .set_user = set_id_aa64zfr0_el1, .visibility = sve_id_visibility },
1488 ID_UNALLOCATED(4,5),
1489 ID_UNALLOCATED(4,6),
1490 ID_UNALLOCATED(4,7),
1491
1492 /* CRm=5 */
1493 ID_SANITISED(ID_AA64DFR0_EL1),
1494 ID_SANITISED(ID_AA64DFR1_EL1),
1495 ID_UNALLOCATED(5,2),
1496 ID_UNALLOCATED(5,3),
1497 ID_HIDDEN(ID_AA64AFR0_EL1),
1498 ID_HIDDEN(ID_AA64AFR1_EL1),
1499 ID_UNALLOCATED(5,6),
1500 ID_UNALLOCATED(5,7),
1501
1502 /* CRm=6 */
1503 ID_SANITISED(ID_AA64ISAR0_EL1),
1504 ID_SANITISED(ID_AA64ISAR1_EL1),
1505 ID_UNALLOCATED(6,2),
1506 ID_UNALLOCATED(6,3),
1507 ID_UNALLOCATED(6,4),
1508 ID_UNALLOCATED(6,5),
1509 ID_UNALLOCATED(6,6),
1510 ID_UNALLOCATED(6,7),
1511
1512 /* CRm=7 */
1513 ID_SANITISED(ID_AA64MMFR0_EL1),
1514 ID_SANITISED(ID_AA64MMFR1_EL1),
1515 ID_SANITISED(ID_AA64MMFR2_EL1),
1516 ID_UNALLOCATED(7,3),
1517 ID_UNALLOCATED(7,4),
1518 ID_UNALLOCATED(7,5),
1519 ID_UNALLOCATED(7,6),
1520 ID_UNALLOCATED(7,7),
1521
1522 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
1523 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
> 1524 { SYS_DESC(SYS_RGSR_EL1), trap_raz_wi, reset_unknown, RGSR_EL1 },
> 1525 { SYS_DESC(SYS_GCR_EL1), trap_raz_wi, reset_unknown, GCR_EL1 },
1526 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
1527 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
1528 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
1529 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
1530
1531 PTRAUTH_KEY(APIA),
1532 PTRAUTH_KEY(APIB),
1533 PTRAUTH_KEY(APDA),
1534 PTRAUTH_KEY(APDB),
1535 PTRAUTH_KEY(APGA),
1536
1537 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
1538 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
1539 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
1540
1541 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
1542 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
1543 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
1544 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
1545 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
1546 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
1547 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
1548 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
1549
> 1550 { SYS_DESC(SYS_TFSR_EL1), trap_raz_wi, reset_unknown, TFSR_EL1 },
> 1551 { SYS_DESC(SYS_TFSRE0_EL1), trap_raz_wi, reset_unknown, TFSRE0_EL1 },
1552
1553 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
1554 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
1555
1556 { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1557 { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
1558
1559 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
1560 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
1561
1562 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
1563 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
1564 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
1565 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
1566 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
1567
1568 { SYS_DESC(SYS_VBAR_EL1), NULL, reset_val, VBAR_EL1, 0 },
1569 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
1570
1571 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
1572 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
1573 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
1574 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
1575 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
1576 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
1577 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
1578 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
1579 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
1580 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
1581 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
1582 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
1583
1584 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
1585 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
1586
1587 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
1588
1589 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
1590 { SYS_DESC(SYS_CLIDR_EL1), access_clidr },
1591 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
1592 { SYS_DESC(SYS_CTR_EL0), access_ctr },
1593
1594 { SYS_DESC(SYS_PMCR_EL0), access_pmcr, reset_pmcr, PMCR_EL0 },
1595 { SYS_DESC(SYS_PMCNTENSET_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1596 { SYS_DESC(SYS_PMCNTENCLR_EL0), access_pmcnten, reset_unknown, PMCNTENSET_EL0 },
1597 { SYS_DESC(SYS_PMOVSCLR_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1598 { SYS_DESC(SYS_PMSWINC_EL0), access_pmswinc, reset_unknown, PMSWINC_EL0 },
1599 { SYS_DESC(SYS_PMSELR_EL0), access_pmselr, reset_unknown, PMSELR_EL0 },
1600 { SYS_DESC(SYS_PMCEID0_EL0), access_pmceid },
1601 { SYS_DESC(SYS_PMCEID1_EL0), access_pmceid },
1602 { SYS_DESC(SYS_PMCCNTR_EL0), access_pmu_evcntr, reset_unknown, PMCCNTR_EL0 },
1603 { SYS_DESC(SYS_PMXEVTYPER_EL0), access_pmu_evtyper },
1604 { SYS_DESC(SYS_PMXEVCNTR_EL0), access_pmu_evcntr },
1605 /*
1606 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
1607 * in 32bit mode. Here we choose to reset it as zero for consistency.
1608 */
1609 { SYS_DESC(SYS_PMUSERENR_EL0), access_pmuserenr, reset_val, PMUSERENR_EL0, 0 },
1610 { SYS_DESC(SYS_PMOVSSET_EL0), access_pmovs, reset_unknown, PMOVSSET_EL0 },
1611
1612 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
1613 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
1614
1615 { SYS_DESC(SYS_AMCR_EL0), access_amu },
1616 { SYS_DESC(SYS_AMCFGR_EL0), access_amu },
1617 { SYS_DESC(SYS_AMCGCR_EL0), access_amu },
1618 { SYS_DESC(SYS_AMUSERENR_EL0), access_amu },
1619 { SYS_DESC(SYS_AMCNTENCLR0_EL0), access_amu },
1620 { SYS_DESC(SYS_AMCNTENSET0_EL0), access_amu },
1621 { SYS_DESC(SYS_AMCNTENCLR1_EL0), access_amu },
1622 { SYS_DESC(SYS_AMCNTENSET1_EL0), access_amu },
1623 AMU_AMEVCNTR0_EL0(0),
1624 AMU_AMEVCNTR0_EL0(1),
1625 AMU_AMEVCNTR0_EL0(2),
1626 AMU_AMEVCNTR0_EL0(3),
1627 AMU_AMEVCNTR0_EL0(4),
1628 AMU_AMEVCNTR0_EL0(5),
1629 AMU_AMEVCNTR0_EL0(6),
1630 AMU_AMEVCNTR0_EL0(7),
1631 AMU_AMEVCNTR0_EL0(8),
1632 AMU_AMEVCNTR0_EL0(9),
1633 AMU_AMEVCNTR0_EL0(10),
1634 AMU_AMEVCNTR0_EL0(11),
1635 AMU_AMEVCNTR0_EL0(12),
1636 AMU_AMEVCNTR0_EL0(13),
1637 AMU_AMEVCNTR0_EL0(14),
1638 AMU_AMEVCNTR0_EL0(15),
1639 AMU_AMEVTYPE0_EL0(0),
1640 AMU_AMEVTYPE0_EL0(1),
1641 AMU_AMEVTYPE0_EL0(2),
1642 AMU_AMEVTYPE0_EL0(3),
1643 AMU_AMEVTYPE0_EL0(4),
1644 AMU_AMEVTYPE0_EL0(5),
1645 AMU_AMEVTYPE0_EL0(6),
1646 AMU_AMEVTYPE0_EL0(7),
1647 AMU_AMEVTYPE0_EL0(8),
1648 AMU_AMEVTYPE0_EL0(9),
1649 AMU_AMEVTYPE0_EL0(10),
1650 AMU_AMEVTYPE0_EL0(11),
1651 AMU_AMEVTYPE0_EL0(12),
1652 AMU_AMEVTYPE0_EL0(13),
1653 AMU_AMEVTYPE0_EL0(14),
1654 AMU_AMEVTYPE0_EL0(15),
1655 AMU_AMEVCNTR1_EL0(0),
1656 AMU_AMEVCNTR1_EL0(1),
1657 AMU_AMEVCNTR1_EL0(2),
1658 AMU_AMEVCNTR1_EL0(3),
1659 AMU_AMEVCNTR1_EL0(4),
1660 AMU_AMEVCNTR1_EL0(5),
1661 AMU_AMEVCNTR1_EL0(6),
1662 AMU_AMEVCNTR1_EL0(7),
1663 AMU_AMEVCNTR1_EL0(8),
1664 AMU_AMEVCNTR1_EL0(9),
1665 AMU_AMEVCNTR1_EL0(10),
1666 AMU_AMEVCNTR1_EL0(11),
1667 AMU_AMEVCNTR1_EL0(12),
1668 AMU_AMEVCNTR1_EL0(13),
1669 AMU_AMEVCNTR1_EL0(14),
1670 AMU_AMEVCNTR1_EL0(15),
1671 AMU_AMEVTYPE1_EL0(0),
1672 AMU_AMEVTYPE1_EL0(1),
1673 AMU_AMEVTYPE1_EL0(2),
1674 AMU_AMEVTYPE1_EL0(3),
1675 AMU_AMEVTYPE1_EL0(4),
1676 AMU_AMEVTYPE1_EL0(5),
1677 AMU_AMEVTYPE1_EL0(6),
1678 AMU_AMEVTYPE1_EL0(7),
1679 AMU_AMEVTYPE1_EL0(8),
1680 AMU_AMEVTYPE1_EL0(9),
1681 AMU_AMEVTYPE1_EL0(10),
1682 AMU_AMEVTYPE1_EL0(11),
1683 AMU_AMEVTYPE1_EL0(12),
1684 AMU_AMEVTYPE1_EL0(13),
1685 AMU_AMEVTYPE1_EL0(14),
1686 AMU_AMEVTYPE1_EL0(15),
1687
1688 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
1689 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
1690 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
1691
1692 /* PMEVCNTRn_EL0 */
1693 PMU_PMEVCNTR_EL0(0),
1694 PMU_PMEVCNTR_EL0(1),
1695 PMU_PMEVCNTR_EL0(2),
1696 PMU_PMEVCNTR_EL0(3),
1697 PMU_PMEVCNTR_EL0(4),
1698 PMU_PMEVCNTR_EL0(5),
1699 PMU_PMEVCNTR_EL0(6),
1700 PMU_PMEVCNTR_EL0(7),
1701 PMU_PMEVCNTR_EL0(8),
1702 PMU_PMEVCNTR_EL0(9),
1703 PMU_PMEVCNTR_EL0(10),
1704 PMU_PMEVCNTR_EL0(11),
1705 PMU_PMEVCNTR_EL0(12),
1706 PMU_PMEVCNTR_EL0(13),
1707 PMU_PMEVCNTR_EL0(14),
1708 PMU_PMEVCNTR_EL0(15),
1709 PMU_PMEVCNTR_EL0(16),
1710 PMU_PMEVCNTR_EL0(17),
1711 PMU_PMEVCNTR_EL0(18),
1712 PMU_PMEVCNTR_EL0(19),
1713 PMU_PMEVCNTR_EL0(20),
1714 PMU_PMEVCNTR_EL0(21),
1715 PMU_PMEVCNTR_EL0(22),
1716 PMU_PMEVCNTR_EL0(23),
1717 PMU_PMEVCNTR_EL0(24),
1718 PMU_PMEVCNTR_EL0(25),
1719 PMU_PMEVCNTR_EL0(26),
1720 PMU_PMEVCNTR_EL0(27),
1721 PMU_PMEVCNTR_EL0(28),
1722 PMU_PMEVCNTR_EL0(29),
1723 PMU_PMEVCNTR_EL0(30),
1724 /* PMEVTYPERn_EL0 */
1725 PMU_PMEVTYPER_EL0(0),
1726 PMU_PMEVTYPER_EL0(1),
1727 PMU_PMEVTYPER_EL0(2),
1728 PMU_PMEVTYPER_EL0(3),
1729 PMU_PMEVTYPER_EL0(4),
1730 PMU_PMEVTYPER_EL0(5),
1731 PMU_PMEVTYPER_EL0(6),
1732 PMU_PMEVTYPER_EL0(7),
1733 PMU_PMEVTYPER_EL0(8),
1734 PMU_PMEVTYPER_EL0(9),
1735 PMU_PMEVTYPER_EL0(10),
1736 PMU_PMEVTYPER_EL0(11),
1737 PMU_PMEVTYPER_EL0(12),
1738 PMU_PMEVTYPER_EL0(13),
1739 PMU_PMEVTYPER_EL0(14),
1740 PMU_PMEVTYPER_EL0(15),
1741 PMU_PMEVTYPER_EL0(16),
1742 PMU_PMEVTYPER_EL0(17),
1743 PMU_PMEVTYPER_EL0(18),
1744 PMU_PMEVTYPER_EL0(19),
1745 PMU_PMEVTYPER_EL0(20),
1746 PMU_PMEVTYPER_EL0(21),
1747 PMU_PMEVTYPER_EL0(22),
1748 PMU_PMEVTYPER_EL0(23),
1749 PMU_PMEVTYPER_EL0(24),
1750 PMU_PMEVTYPER_EL0(25),
1751 PMU_PMEVTYPER_EL0(26),
1752 PMU_PMEVTYPER_EL0(27),
1753 PMU_PMEVTYPER_EL0(28),
1754 PMU_PMEVTYPER_EL0(29),
1755 PMU_PMEVTYPER_EL0(30),
1756 /*
1757 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
1758 * in 32bit mode. Here we choose to reset it as zero for consistency.
1759 */
1760 { SYS_DESC(SYS_PMCCFILTR_EL0), access_pmu_evtyper, reset_val, PMCCFILTR_EL0, 0 },
1761
1762 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
1763 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
1764 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
1765 };
1766

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

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