Re: [PATCH v2 2/2] phy: socionext: Add UniPhier AHCI PHY driver support

[Kunihiko Hayashi]

Hi Vinod,

On 2020/07/13 14:05, Vinod Koul wrote:
> On 30-06-20, 17:59, Kunihiko Hayashi wrote:
>
> > +++ b/drivers/phy/socionext/phy-uniphier-ahci.c
> > @@ -0,0 +1,335 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller
> > + * Copyright 2016-2018, Socionext Inc.
>
> we are in 2020 now!

Oops, I'll adjust it.

> > +static int uniphier_ahciphy_pxs2_power_on(struct uniphier_ahciphy_priv *priv)
> > +{
> > +	int ret;
> > +	u32 val;
> > +
> > +	/* enable reference clock for PHY */
> > +	val = readl(priv->base + CKCTRL);
> > +	val |= CKCTRL_REF_SSP_EN;
> > +	writel(val, priv->base + CKCTRL);
> > +
> > +	/* release port reset */
> > +	val = readl(priv->base + CKCTRL);
> > +	val &= ~CKCTRL_P0_RESET;
> > +	writel(val, priv->base + CKCTRL);
> > +
> > +	/* wait until PLL is ready */
> > +	if (priv->data->is_ready_high)
> > +		ret = readl_poll_timeout(priv->base + CKCTRL, val,
> > +					 (val & CKCTRL_P0_READY), 200, 400);
> > +	else
> > +		ret = readl_poll_timeout(priv->base + CKCTRL, val,
> > +					 !(val & CKCTRL_P0_READY), 200, 400);
> > +	if (ret) {
> > +		dev_err(priv->dev, "Failed to check whether PHY PLL is ready\n");
> > +		goto out_disable_clock;
> > +	}
> > +
> > +	return 0;
> > +
> > +out_disable_clock:
> > +	/* assert port reset */
> > +	val = readl(priv->base + CKCTRL);
> > +	val |= CKCTRL_P0_RESET;
> > +	writel(val, priv->base + CKCTRL);
> > +
> > +	/* disable reference clock for PHY */
> > +	val = readl(priv->base + CKCTRL);
> > +	val &= ~CKCTRL_REF_SSP_EN;
> > +	writel(val, priv->base + CKCTRL);
>
> this seems to be repeated patter, why not add a modifyl() helper here..

Hmm, I try to add helpers for modifying P0_RESET and REF_SSP_EN bits.

> > +static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv)
> > +{
> > +	int i;
> > +	u32 val;
> > +
> > +	/* setup port parameter */
> > +	val = readl(priv->base + TXCTRL0);
> > +	val &= ~TXCTRL0_AMP_G3_MASK;
> > +	val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73);
> > +	val &= ~TXCTRL0_AMP_G2_MASK;
> > +	val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46);
> > +	val &= ~TXCTRL0_AMP_G1_MASK;
> > +	val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42);
> > +	writel(val, priv->base + TXCTRL0);
> > +
> > +	val = readl(priv->base + TXCTRL1);
> > +	val &= ~TXCTRL1_DEEMPH_G3_MASK;
> > +	val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23);
> > +	val &= ~TXCTRL1_DEEMPH_G2_MASK;
> > +	val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05);
> > +	val &= ~TXCTRL1_DEEMPH_G1_MASK;
> > +	val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05);
> > +
> > +	val = readl(priv->base + RXCTRL);
> > +	val &= ~RXCTRL_LOS_LVL_MASK;
> > +	val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9);
> > +	val &= ~RXCTRL_LOS_BIAS_MASK;
> > +	val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2);
> > +	val &= ~RXCTRL_RX_EQ_MASK;
> > +	val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1);
> > +
> > +	/* dummy read 25 times */
>
> why?

According to the specification document,
these 25 read accesses make a wait time for the phy to stablize.
I'll add the reason as comment.

> > +static int uniphier_ahciphy_init(struct phy *phy)
> > +{
> > +	struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy);
> > +	int ret;
> > +
> > +	ret = clk_prepare_enable(priv->clk_parent);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = reset_control_deassert(priv->rst_parent);
> > +	if (ret)
> > +		goto out_clk_disable;
> > +
> > +	if (priv->data->init) {
> > +		ret = priv->data->init(priv);
> > +		if (ret)
> > +			goto out_rst_assert;
> > +	}
> > +
> > +	return ret;
>
> return 0?

Yes, I'll fix it.

> > +static const struct uniphier_ahciphy_soc_data uniphier_pxs2_data = {
> > +	.init = NULL,
>
> Isn't this superfluous ?

Indeed, this can be removed.

Thank you,

---
Best Regards
Kunihiko Hayashi