Re: [PATCH V6 07/14] perf/x86/intel: Generic support for hardware TopDown metrics

[Peter Zijlstra]

On Fri, Jul 17, 2020 at 07:05:47AM -0700, kan.liang@xxxxxxxxxxxxxxx wrote:

> For the event mapping, a special 0x00 event code is used, which is
> reserved for fake events. The metric events start from umask 0x10.

> +#define INTEL_PMC_IDX_METRIC_BASE		(INTEL_PMC_IDX_FIXED + 16)
> +#define INTEL_PMC_IDX_TD_RETIRING		(INTEL_PMC_IDX_METRIC_BASE + 0)
> +#define INTEL_PMC_IDX_TD_BAD_SPEC		(INTEL_PMC_IDX_METRIC_BASE + 1)
> +#define INTEL_PMC_IDX_TD_FE_BOUND		(INTEL_PMC_IDX_METRIC_BASE + 2)
> +#define INTEL_PMC_IDX_TD_BE_BOUND		(INTEL_PMC_IDX_METRIC_BASE + 3)

So this is internal and we can change it around if/when needed, right?

> +#define INTEL_PMC_IDX_METRIC_END		INTEL_PMC_IDX_TD_BE_BOUND
> +#define INTEL_PMC_MSK_TOPDOWN			((0xfull << INTEL_PMC_IDX_METRIC_BASE) | \
> +						INTEL_PMC_MSK_FIXED_SLOTS)
> +
> +/*
> + * There is no event-code assigned to the TopDown events.
> + *
> + * For the slots event, use the pseudo code of the fixed counter 3.
> + *
> + * For the metric events, the pseudo event-code is 0x00.
> + * The pseudo umask-code starts from 0x10.
> + */
> +#define INTEL_TD_SLOTS				0x0400	/* TOPDOWN.SLOTS */
> +/* Level 1 metrics */
> +#define INTEL_TD_METRIC_RETIRING		0x1000	/* Retiring metric */
> +#define INTEL_TD_METRIC_BAD_SPEC		0x1100	/* Bad speculation metric */
> +#define INTEL_TD_METRIC_FE_BOUND		0x1200	/* FE bound metric */
> +#define INTEL_TD_METRIC_BE_BOUND		0x1300	/* BE bound metric */
> +#define INTEL_TD_METRIC_MAX			INTEL_TD_METRIC_BE_BOUND
> +#define INTEL_TD_METRIC_NUM			4

But this is ABI, once we merge this, it's stuck.

Also, per how Fixed2 is 0x0300, should not Fixed16 (aka
METRICS_RETIRING) be 0x1100 ?

But aside of that, are we sure the hardware will never grow a Fixed16?
Or do we want to be paranoid and move the metrics events up in the
pseudo event space?