Re: [PATCH v9 08/10] gpu: host1x: mipi: Keep MIPI clock enabled and mutex locked till calibration done

[Sowjanya Komatineni]

On 8/6/20 8:10 PM, Sowjanya Komatineni wrote:
> On 8/6/20 7:31 PM, Dmitry Osipenko wrote:
> > 06.08.2020 22:01, Sowjanya Komatineni пишет:
> > ...
> > > +int tegra_mipi_start_calibration(struct tegra_mipi_device *device)
> > >   {
> > >       const struct tegra_mipi_soc *soc = device->mipi->soc;
> > >       unsigned int i;
> > > @@ -381,12 +375,16 @@ int tegra_mipi_calibrate(struct 
> > > tegra_mipi_device *device)
> > >       value |= MIPI_CAL_CTRL_START;
> > >       tegra_mipi_writel(device->mipi, value, MIPI_CAL_CTRL);
> > >   -    mutex_unlock(&device->mipi->lock);
> > > -    clk_disable(device->mipi->clk);
> > > +    /*
> > > +     * Wait for min 72uS to let calibration logic finish calibration
> > > +     * sequence codes before waiting for pads idle state to apply the
> > > +     * results.
> > > +     */
> > > +    usleep_range(75, 80);
> > Could you please explain why the ACTIVE bit can't be polled instead of
> > using the fixed delay? Doesn't ACTIVE bit represents the state of the
> > busy FSM?
>
> Based on internal discussion, ACTIVE bit gets cleared when all enabled 
> pads calibration is done (same time as when DONE set to 1).
>
> Will request HW designer to look into design and confirm  exactly when 
> ACTIVE bit gets cleared.
>
> Will get back on this.
Verified with HW designer. above is correct. ACTIVE bit update happens 
same time as DONE bit.

Active = !(DONE)

In case of calibration logic waiting for LP-11 where done bit does not 
get set, ACTIVE will still be 1 and on next start trigger new 
calibration will start

>