drivers/gpu/drm/nouveau/nouveau_bo5039.c:39 nv50_bo_move_m2mf() warn: should 'new_reg->num_pages << 12' be a 64 bit
From: kernel test robot
Date: Fri Aug 07 2020 - 13:49:04 EST
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 86cfccb66937dd6cbf26ed619958b9e587e6a115
commit: 8b9d5d63a7193156b6b397c4f5078efbc200695f drm/nouveau/bo: split buffer move functions into their own source files
date: 2 weeks ago
config: i386-randconfig-m021-20200807 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>
smatch warnings:
drivers/gpu/drm/nouveau/nouveau_bo5039.c:39 nv50_bo_move_m2mf() warn: should 'new_reg->num_pages << 12' be a 64 bit type?
vim +39 drivers/gpu/drm/nouveau/nouveau_bo5039.c
33
34 int
35 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
36 struct ttm_mem_reg *old_reg, struct ttm_mem_reg *new_reg)
37 {
38 struct nouveau_mem *mem = nouveau_mem(old_reg);
> 39 u64 length = (new_reg->num_pages << PAGE_SHIFT);
40 u64 src_offset = mem->vma[0].addr;
41 u64 dst_offset = mem->vma[1].addr;
42 int src_tiled = !!mem->kind;
43 int dst_tiled = !!nouveau_mem(new_reg)->kind;
44 int ret;
45
46 while (length) {
47 u32 amount, stride, height;
48
49 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
50 if (ret)
51 return ret;
52
53 amount = min(length, (u64)(4 * 1024 * 1024));
54 stride = 16 * 4;
55 height = amount / stride;
56
57 if (src_tiled) {
58 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
59 OUT_RING (chan, 0);
60 OUT_RING (chan, 0);
61 OUT_RING (chan, stride);
62 OUT_RING (chan, height);
63 OUT_RING (chan, 1);
64 OUT_RING (chan, 0);
65 OUT_RING (chan, 0);
66 } else {
67 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
68 OUT_RING (chan, 1);
69 }
70 if (dst_tiled) {
71 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
72 OUT_RING (chan, 0);
73 OUT_RING (chan, 0);
74 OUT_RING (chan, stride);
75 OUT_RING (chan, height);
76 OUT_RING (chan, 1);
77 OUT_RING (chan, 0);
78 OUT_RING (chan, 0);
79 } else {
80 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
81 OUT_RING (chan, 1);
82 }
83
84 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
85 OUT_RING (chan, upper_32_bits(src_offset));
86 OUT_RING (chan, upper_32_bits(dst_offset));
87 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
88 OUT_RING (chan, lower_32_bits(src_offset));
89 OUT_RING (chan, lower_32_bits(dst_offset));
90 OUT_RING (chan, stride);
91 OUT_RING (chan, stride);
92 OUT_RING (chan, stride);
93 OUT_RING (chan, height);
94 OUT_RING (chan, 0x00000101);
95 OUT_RING (chan, 0x00000000);
96 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
97 OUT_RING (chan, 0);
98
99 length -= amount;
100 src_offset += amount;
101 dst_offset += amount;
102 }
103
104 return 0;
105 }
106
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.config.gz
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