Re: [PATCH] drm/amd/display: remove unintended executable mode

[Christian König]

Am 19.08.20 um 10:18 schrieb Lukas Bulwahn:
> Besides the intended change, commit 4cc1178e166a ("drm/amdgpu: replace DRM
> prefix with PCI device info for gfx/mmhub") also set the source files
> mmhub_v1_0.c and gfx_v9_4.c to be executable, i.e., changed fromold mode
> 644 to new mode 755.
>
> Commit 241b2ec9317e ("drm/amd/display: Add dcn30 Headers (v2)") added the
> four header files {dpcs,dcn}_3_0_0_{offset,sh_mask}.h as executable, i.e.,
> mode 755.
>
> Set to the usual modes for source and headers files and clean up those
> mistakes. No functional change.
>
> Signed-off-by: Lukas Bulwahn <lukas.bulwahn@xxxxxxxxx>

Reviewed-by: Christian König <christian.koenig@xxxxxxx>

> ---
> applies cleanly on current master and next-20200819
>
> Alex, Christian, please pick this minor non-urgent cleanup patch.

Alex is usually the one picking those up. If he misses something feel 
free to ping us once more.

Thanks,
Christian.

> Dennis, Jerry, please ack.
>
> Dennis, Jerry, you might want to check your development environment
> introducing those executable modes on files.
>
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c                         | 0
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c                       | 0
>   drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h   | 0
>   drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h  | 0
>   drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h  | 0
>   drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h | 0
>   6 files changed, 0 insertions(+), 0 deletions(-)
>   mode change 100755 => 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
>   mode change 100755 => 100644 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>   mode change 100755 => 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
>   mode change 100755 => 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
>   mode change 100755 => 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h
>   mode change 100755 => 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4.c
> old mode 100755
> new mode 100644
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> old mode 100755
> new mode 100644
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_offset.h
> old mode 100755
> new mode 100644
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_0_0_sh_mask.h
> old mode 100755
> new mode 100644
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_offset.h
> old mode 100755
> new mode 100644
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_3_0_0_sh_mask.h
> old mode 100755
> new mode 100644