Re: [PATCH 1/2] hwmon: (k10temp) Create common functions and macros for Zen CPU families

From: Guenter Roeck
Date: Thu Aug 27 2020 - 15:52:44 EST

On Thu, Aug 27, 2020 at 12:42:41AM -0500, Wei Huang wrote:
> Many SMN thermal registers in Zen CPU families are common across different
> generations. For long-term code maintenance, it is better to rename these
> macro and function names to Zen.
>
> Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>

Applied.

Thanks,
Guenter

> ---
> drivers/hwmon/k10temp.c | 56 +++++++++++++++++++++--------------------
> 1 file changed, 29 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
> index 8f12995ec133..f3addb97b021 100644
> --- a/drivers/hwmon/k10temp.c
> +++ b/drivers/hwmon/k10temp.c
> @@ -73,22 +73,24 @@ static DEFINE_MUTEX(nb_smu_ind_mutex);
> #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
> #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
>
> -/* F17h M01h Access througn SMN */
> -#define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
> +/* Common for Zen CPU families (Family 17h and 18h) */
> +#define ZEN_REPORTED_TEMP_CTRL_OFFSET 0x00059800
>
> -#define F17H_M70H_CCD_TEMP(x) (0x00059954 + ((x) * 4))
> -#define F17H_M70H_CCD_TEMP_VALID BIT(11)
> -#define F17H_M70H_CCD_TEMP_MASK GENMASK(10, 0)
> +#define ZEN_CCD_TEMP(x) (0x00059954 + ((x) * 4))
> +#define ZEN_CCD_TEMP_VALID BIT(11)
> +#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
>
> -#define F17H_M01H_SVI 0x0005A000
> -#define F17H_M01H_SVI_TEL_PLANE0 (F17H_M01H_SVI + 0xc)
> -#define F17H_M01H_SVI_TEL_PLANE1 (F17H_M01H_SVI + 0x10)
> +#define ZEN_CUR_TEMP_SHIFT 21
> +#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
>
> -#define CUR_TEMP_SHIFT 21
> -#define CUR_TEMP_RANGE_SEL_MASK BIT(19)
> +#define ZEN_SVI_BASE 0x0005A000
>
> -#define CFACTOR_ICORE 1000000 /* 1A / LSB */
> -#define CFACTOR_ISOC 250000 /* 0.25A / LSB */
> +/* F17h thermal registers through SMN */
> +#define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
> +#define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
> +
> +#define F17H_CFACTOR_ICORE 1000000 /* 1A / LSB */
> +#define F17H_CFACTOR_ISOC 250000 /* 0.25A / LSB */
>
> struct k10temp_data {
> struct pci_dev *pdev;
> @@ -168,10 +170,10 @@ static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
> F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
> }
>
> -static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
> +static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
> {
> amd_smn_read(amd_pci_dev_to_node_id(pdev),
> - F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
> + ZEN_REPORTED_TEMP_CTRL_OFFSET, regval);
> }
>
> static long get_raw_temp(struct k10temp_data *data)
> @@ -180,7 +182,7 @@ static long get_raw_temp(struct k10temp_data *data)
> long temp;
>
> data->read_tempreg(data->pdev, &regval);
> - temp = (regval >> CUR_TEMP_SHIFT) * 125;
> + temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
> if (regval & data->temp_adjust_mask)
> temp -= 49000;
> return temp;
> @@ -288,8 +290,8 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
> break;
> case 2 ... 9: /* Tccd{1-8} */
> amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
> - F17H_M70H_CCD_TEMP(channel - 2), &regval);
> - *val = (regval & F17H_M70H_CCD_TEMP_MASK) * 125 - 49000;
> + ZEN_CCD_TEMP(channel - 2), &regval);
> + *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
> break;
> default:
> return -EOPNOTSUPP;
> @@ -438,7 +440,7 @@ static int svi_show(struct seq_file *s, void *unused)
> {
> struct k10temp_data *data = s->private;
>
> - k10temp_smn_regs_show(s, data->pdev, F17H_M01H_SVI, 32);
> + k10temp_smn_regs_show(s, data->pdev, ZEN_SVI_BASE, 32);
> return 0;
> }
> DEFINE_SHOW_ATTRIBUTE(svi);
> @@ -448,7 +450,7 @@ static int thm_show(struct seq_file *s, void *unused)
> struct k10temp_data *data = s->private;
>
> k10temp_smn_regs_show(s, data->pdev,
> - F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, 256);
> + ZEN_REPORTED_TEMP_CTRL_OFFSET, 256);
> return 0;
> }
> DEFINE_SHOW_ATTRIBUTE(thm);
> @@ -528,8 +530,8 @@ static void k10temp_get_ccd_support(struct pci_dev *pdev,
>
> for (i = 0; i < limit; i++) {
> amd_smn_read(amd_pci_dev_to_node_id(pdev),
> - F17H_M70H_CCD_TEMP(i), &regval);
> - if (regval & F17H_M70H_CCD_TEMP_VALID)
> + ZEN_CCD_TEMP(i), &regval);
> + if (regval & ZEN_CCD_TEMP_VALID)
> data->show_temp |= BIT(TCCD_BIT(i));
> }
> }
> @@ -565,8 +567,8 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> data->read_htcreg = read_htcreg_nb_f15;
> data->read_tempreg = read_tempreg_nb_f15;
> } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
> - data->temp_adjust_mask = CUR_TEMP_RANGE_SEL_MASK;
> - data->read_tempreg = read_tempreg_nb_f17;
> + data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
> + data->read_tempreg = read_tempreg_nb_zen;
> data->show_temp |= BIT(TDIE_BIT); /* show Tdie */
> data->is_zen = true;
>
> @@ -578,15 +580,15 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
> data->show_current = !is_threadripper() && !is_epyc();
> data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE0;
> data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE1;
> - data->cfactor[0] = CFACTOR_ICORE;
> - data->cfactor[1] = CFACTOR_ISOC;
> + data->cfactor[0] = F17H_CFACTOR_ICORE;
> + data->cfactor[1] = F17H_CFACTOR_ISOC;
> k10temp_get_ccd_support(pdev, data, 4);
> break;
> case 0x31: /* Zen2 Threadripper */
> case 0x71: /* Zen2 */
> data->show_current = !is_threadripper() && !is_epyc();
> - data->cfactor[0] = CFACTOR_ICORE;
> - data->cfactor[1] = CFACTOR_ISOC;
> + data->cfactor[0] = F17H_CFACTOR_ICORE;
> + data->cfactor[1] = F17H_CFACTOR_ISOC;
> data->svi_addr[0] = F17H_M01H_SVI_TEL_PLANE1;
> data->svi_addr[1] = F17H_M01H_SVI_TEL_PLANE0;
> k10temp_get_ccd_support(pdev, data, 8);