Re: [PATCH] x86/msr: do not warn on writes to OC_MAILBOX

[Borislav Petkov]

On Mon, Sep 07, 2020 at 01:15:14PM +0200, Jason A. Donenfeld wrote:
> Gotcha. So your perspective is that the goal is actually to have no
> list at all in the end, because all MSR writes should go through sysfs
> interfaces and such, always? I certainly like that goal -- it'd make a
> whole lot of CPU functionality a lot more discoverable and easier to
> tinker with. In practice, it seems like that's a hard goal to
> accomplish, with different MSRs having different semantics and
> meanings of different bit offsets, and a great deal of them aren't
> actually publicly documented by Intel. Were you hoping to just handle
> these piece by piece, and eventually Linux will have a decent
> compendium of MSRs? That sure would be nice.

Yes to all of the above.

The MSRs should not have been exposed to userspace in the first place.
See the commit message of:

  a7e1f67ed29f ("x86/msr: Filter MSR writes")

for why not.

> Is Intel on board with that plan?

They better be. Like the other vendors who have MSRs too.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette