Re: [PATCH v2 2/3] soc: sifive: Add SiFive specific Cadence DDR controller driver

From: Palmer Dabbelt
Date: Wed Sep 09 2020 - 16:31:12 EST

On Tue, 08 Sep 2020 23:00:45 PDT (-0700), Christoph Hellwig wrote:
On Tue, Sep 08, 2020 at 08:12:16PM -0700, Palmer Dabbelt wrote:
I don't know enough about the block to know if the subtle difference in
register names/offsets means. They look properly jumbled up (ie, not just an
offset), so maybe there's just different versions or that's the SiFive-specific
part I had bouncing around my head? Either way, it seems like one driver with
some simple configuration could handle both of these -- either sticking the
offsets in the DT (if they're going to be different everywhere) or by coming up
with some version sort of thing (if there's a handful of these).

regmap can be used to handle non-uniform register layouts for the same

Ah, cool, I hadn't seen that before. That seems like the way to go if this is
truly an implementatic-specific register mapping. As I was falling asleep last
night I remembered that we did end up with implementation-specific register
maps for some of the IP we integrated. That was usually the case for IP where
we had some signals that we just didn't know what to do with, and while I know
the DDR integration was a real trip I'm not sure if that's where these
registers came from.

Hopefully someone who has better access to these hardware implementations can