[RFC PATCH v7 00/21] riscv: Add vector ISA support

From: Greentime Hu
Date: Thu Sep 10 2020 - 04:13:35 EST

This patchset is implemented based on vector 0.9+ spec to add vector support
in riscv Linux kernel. To make this happen, we defined a new structure
__riscv_v_state to save the vector related registers. It is used for both
kernel space and user space. In kernel space, the datap pointer in
__riscv_v_state will be allocated dynamically to save vector registers.
In signal handler of user space, datap will point to the address right
after the __riscv_v_state data structure to save vector registers in stack.
In ptrace, the data will be put in ubuf in which we can get/put the
__riscv_v_state data structure from/to it, datap pointer would be zeroed and
vector registers will be copied to the address right after the
__riscv_v_state structure in ubuf. This patchset also adds support for kernel
mode vector, kernel XOR implementation with vector ISA and includes several
bug fixes and code refinement.

This patchset is rebased to v5.9-rc4 and it is tested by running several
vector programs simultaneously. It also can get the correct ucontext_t in
signal handler and restore correct context after sigreturn. It is also
tested with ptrace() syscall to use PTRACE_GETREGSET/PTRACE_SETREGSET to
get/set the vector registers. I have tested vlen=128 and vlen=256 cases in
spike machine of qemu-system-riscv64 provided by Zhiwei Lui and Frank Chang
and also tested in spike with vlen=64 to vlen=4096 settings.

We also sent patches to glibc mailing list for ifunc support and sigcontext

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
[2] https://github.com/sifive/qemu/tree/rvv-1.0-upstream-v4
[3] https://blog.linuxplumbersconf.org/2017/ocw/sessions/4671.html
[4] https://sourceware.org/pipermail/libc-alpha/2020-July/116059.html
[5] https://sourceware.org/pipermail/libc-alpha/2020-July/116108.html
[6] https://linuxplumbersconf.org/event/7/contributions/811/

Changelog V7
- Add support for kernel mode vector
- Add vector extension XOR implementation
- Optimize task switch codes of vector
- Allocate space for vector registers in start_thread()
- Fix an illegal instruction exception when accessing vlenb
- Optimize vector registers initialization
- Initialize vector registers with proper vsetvli then it can work normally
- Refine ptrace porting due to generic API changed
- Code clean up

Changelog V6
- Replace vle.v/vse.v instructions with vle8.v/vse8.v based on 0.9 spec
- Add comments based on mailinglist feedback
- Fix rv32 build error

Changelog V5
- Using regset_size() correctly in generic ptrace
- Fix the ptrace porting
- Fix compile warning

Changelog V4
- Support dynamic vlen
- Fix bugs: lazy save/resotre, not saving vtype
- Update VS bit offset based on latest vector spec
- Add new vector csr based on latest vector spec
- Code refine and removed unused macros

Changelog V3
- Rebase linux-5.6-rc3 and tested with qemu
- Seperate patches with Anup's advice
- Give out a ABI puzzle with unlimited vlen

Changelog V2
- Fixup typo "vecotr, fstate_save->vstate_save".
- Fixup wrong saved registers' length in vector.S.
- Seperate unrelated patches from this one.

Greentime Hu (16):
riscv: Extending cpufeature.c to detect V-extension
riscv: Add new csr defines related to vector extension
riscv: Add has_vector/riscv_vsize to save vector features.
riscv: Add vector struct and assembler definitions
riscv: Add task switch support for vector
riscv: Add task switch support for vector
riscv: Add ptrace vector support
riscv: Add sigcontext save/restore for vector
riscv: Add support for kernel mode vector
riscv: Use CSR_STATUS to replace sstatus in vector.S
riscv: Add vector extension XOR implementation
riscv: Initialize vector registers with proper vsetvli then it can
work normally
riscv: Optimize vector registers initialization
riscv: Fix an illegal instruction exception when accessing vlenb
without enable vector first
riscv: Allocate space for vector registers in start_thread()
riscv: Optimize task switch codes of vector

Guo Ren (4):
riscv: Separate patch for cflags and aflags
riscv: Rename __switch_to_aux -> fpu
riscv: Add vector feature to compile
riscv: Reset vector register

Vincent Chen (1):
riscv: signal: Report signal frame size to userspace via auxv

arch/riscv/Kconfig | 9 ++
arch/riscv/Makefile | 19 ++-
arch/riscv/include/asm/csr.h | 16 ++-
arch/riscv/include/asm/elf.h | 17 ++-
arch/riscv/include/asm/processor.h | 3 +
arch/riscv/include/asm/switch_to.h | 67 +++++++++-
arch/riscv/include/asm/vector.h | 18 +++
arch/riscv/include/asm/xor.h | 74 +++++++++++
arch/riscv/include/uapi/asm/auxvec.h | 2 +
arch/riscv/include/uapi/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/ptrace.h | 31 +++++
arch/riscv/include/uapi/asm/sigcontext.h | 2 +
arch/riscv/kernel/Makefile | 7 +
arch/riscv/kernel/asm-offsets.c | 8 ++
arch/riscv/kernel/cpufeature.c | 16 +++
arch/riscv/kernel/entry.S | 6 +-
arch/riscv/kernel/head.S | 22 +++-
arch/riscv/kernel/kernel_mode_vector.c | 158 +++++++++++++++++++++++
arch/riscv/kernel/process.c | 48 +++++++
arch/riscv/kernel/ptrace.c | 74 +++++++++++
arch/riscv/kernel/setup.c | 5 +
arch/riscv/kernel/signal.c | 108 +++++++++++++++-
arch/riscv/kernel/vector.S | 81 ++++++++++++
arch/riscv/lib/Makefile | 1 +
arch/riscv/lib/xor.S | 81 ++++++++++++
include/uapi/linux/elf.h | 1 +
26 files changed, 852 insertions(+), 23 deletions(-)
create mode 100644 arch/riscv/include/asm/vector.h
create mode 100644 arch/riscv/include/asm/xor.h
create mode 100644 arch/riscv/kernel/kernel_mode_vector.c
create mode 100644 arch/riscv/kernel/vector.S
create mode 100644 arch/riscv/lib/xor.S