Re: [PATCH] gpio: dwapb: add support for new hisilicon ascend soc

[Serge Semin]

On Sun, Sep 06, 2020 at 06:18:07AM +0000, Dingtianhong wrote:

[...]

> > On Sat, Aug 22, 2020 at 12:27:53PM +0800, Ding Tianhong wrote:
> >> The hisilicon ascend soc's gpio is based on the synopsys DW gpio,
> >> and expand the register to support for INTCOMB_MASK, the new
> >> register is used to enable/disable the interrupt combine features.
> > 
> > I am wondering what does the "Interrupt Combine" feature do? Is it the same as
> > the GPIO_INTR_IO pre-synthesize parameter of the DW_apb_gpio IP-core? Is it
> > possible to tune the DW APB GPIO controller at runtime sending up to the IRQ
> > controller either combined or individual interrupts?
> > 
> 
> looks like the same.
> 
> > If the later is true, then probably having the "Interrupt Combine" feature
> > enabled must depend on whether an individual or combined interrupts are supplied
> > in dts, etc...
> > 
> 
> needed.
> 
> > Could you explain the way the feature works and the corresponding layout
> > register in more details?
> > 
> 
> Ok
> The hisilicon chip use the register called GPIO_INTCOMB_MASK (offset is 0xffc) to enable the combien interrupt.
> it is very simple, if GPIO_INTCOMB_MASK.bit0 is 0, then all combine interrupte could not be used (default
> setting), otherwise if 1, then the 32 ports could use the same irq line, that is all.

The main question is whether your hardware is capable of working with both
combined and individual interrupts. Is your version of the DW APB GPIO
controller able to generate both types of them? How is it connected to the
parental interrupt controller?

So If the GPIO and IRQ controllers are attached to each other with a single lane
gpio_intr_flag, then indeed it's pure combined IRQ design and we'll have to make
sure that GPIO_INTCOMB_MASK.bit0 is set to one before using the DW GPIO block.
If they are also connected with each other by 32 individual GPIO-IRQ
gpio_intr{_n}N lanes, then setting or clearing of the GPIO_INTCOMB_MASK.bit0
flag will for example depend on the number IRQ lanes specified in a dts file. In
the later case the patch needs to be altered, but it would provide a better
support of the hisilicon ascend soc's GPIO capabilities.

-Sergey