[PATCH v3 1/2] ARM: fix trivial comments in head.S

[Zhen Lei]

1. Change pv_offset to __pv_offset.
2. Change PHYS_OFFSET to PHYS_PFN_OFFSET.
   commit e26a9e00afc4 ("ARM: Better virt_to_page() handling") replaced
   __pv_phys_offset with __pv_phys_pfn_offset, but forgot updating the
   related PHYS_OFFSET to PHYS_PFN_OFFSET.
   #define PHYS_PFN_OFFSET   (__pv_phys_pfn_offset)

Fixes: f52bb722547f ("ARM: mm: Correct virt_to_phys patching for 64 bit physical addresses")
Fixes: e26a9e00afc4 ("ARM: Better virt_to_page() handling")
Signed-off-by: Zhen Lei <thunder.leizhen@xxxxxxxxxx>
---
 arch/arm/kernel/head.S | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index f8904227e7fdc44..02d78c9198d0e8d 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -612,7 +612,7 @@ __fixup_pv_table:
 	add	r6, r6, r3	@ adjust __pv_phys_pfn_offset address
 	add	r7, r7, r3	@ adjust __pv_offset address
 	mov	r0, r8, lsr #PAGE_SHIFT	@ convert to PFN
-	str	r0, [r6]	@ save computed PHYS_OFFSET to __pv_phys_pfn_offset
+	str	r0, [r6]	@ save computed PHYS_PFN_OFFSET to __pv_phys_pfn_offset
 	strcc	ip, [r7, #HIGH_OFFSET]	@ save to __pv_offset high bits
 	mov	r6, r3, lsr #24	@ constant for add/sub instructions
 	teq	r3, r6, lsl #24 @ must be 16MiB aligned
@@ -634,8 +634,8 @@ __fixup_a_pv_table:
 	adr	r0, 3f
 	ldr	r6, [r0]
 	add	r6, r6, r3
-	ldr	r0, [r6, #HIGH_OFFSET]	@ pv_offset high word
-	ldr	r6, [r6, #LOW_OFFSET]	@ pv_offset low word
+	ldr	r0, [r6, #HIGH_OFFSET]	@ __pv_offset high word
+	ldr	r6, [r6, #LOW_OFFSET]	@ __pv_offset low word
 	mov	r6, r6, lsr #24
 	cmn	r0, #1
 #ifdef CONFIG_THUMB2_KERNEL
-- 
1.8.3