[PATCH 4.4 35/46] MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

From: Greg Kroah-Hartman
Date: Mon Sep 21 2020 - 12:33:53 EST


From: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>

[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]

Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@xxxxxxxxxxxxxxxx>
Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>
---
arch/mips/Kconfig | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 596cbda9cb3d3..9d8bc19edc48e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -817,6 +817,7 @@ config SNI_RM
select I8253
select I8259
select ISA
+ select MIPS_L1_CACHE_SHIFT_6
select SWAP_IO_SPACE if CPU_BIG_ENDIAN
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_R5000
--
2.25.1