Re: [PATCH v2 1/4] dt-bindings: mmc: Convert mtk-sd to json-schema

[Wenbin Mei]

Thanks for your reply!
I will change the following problems in the next version.

On Tue, 2020-09-29 at 15:05 -0500, Rob Herring wrote:
> On Mon, Sep 28, 2020 at 09:09:15PM +0800, Wenbin Mei wrote:
> > Convert the mtk-sd binding to DT schema format using json-schema.
> > 
> > Signed-off-by: Wenbin Mei <wenbin.mei@xxxxxxxxxxxx>
> > Reviewed-by: Ulf Hansson <ulf.hansson@xxxxxxxxxx>
> > ---
> >  .../devicetree/bindings/mmc/mtk-sd.txt        |  75 --------
> >  .../devicetree/bindings/mmc/mtk-sd.yaml       | 165 ++++++++++++++++++
> >  2 files changed, 165 insertions(+), 75 deletions(-)
> >  delete mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.txt
> >  create mode 100644 Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> 
> 
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > new file mode 100644
> > index 000000000000..2d5ab1411cd5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -0,0 +1,165 @@
> > +# MTK-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MTK MSDC Storage Host Controller Binding
> > +
> > +maintainers:
> > +  - Ulf Hansson <ulf.hansson@xxxxxxxxxx>
> 
> Usually this is the h/w block owner, not a subsystem maintainer.
> 
> > +
> > +allOf:
> > +  - $ref: mmc-controller.yaml#
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - const: mediatek,mt8135-mmc
> > +      - const: mediatek,mt8173-mmc
> > +      - const: mediatek,mt8183-mmc
> > +      - const: mediatek,mt8516-mmc
> > +      - const: mediatek,mt6779-mmc
> > +      - const: mediatek,mt2701-mmc
> > +      - const: mediatek,mt2712-mmc
> > +      - const: mediatek,mt7622-mmc
> 
> All these can be an enum. And sort please.
> 
> > +      - items:
> > +        - const: mediatek,mt7623-mmc
> > +        - const: mediatek,mt2701-mmc
> > +      - const: mediatek,mt7620-mmc
> > +
> > +  reg:
> > +    description:
> > +      physical base address of the controller and length.
> 
> Drop this.
> 
> > +    minItems: 1
> > +    maxItems: 2
> 
> If more than 1, need to say what each entry is:
> 
> items:
>   - description: ...
>   - description: ...
> 
> > +
> > +  interrupts:
> > +    description:
> > +      Should contain MSDC interrupt number.
> 
> Drop.
> 
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    description:
> > +      Should contain phandle for the clock feeding the MMC controller.
> > +    minItems: 2
> > +    maxItems: 4
> > +    items:
> > +      - description: source clock (required).
> > +      - description: HCLK which used for host (required).
> > +      - description: independent source clock gate (required for MT2712).
> > +      - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
> > +
> > +  clock-names:
> > +    minItems: 2
> > +    maxItems: 4
> > +    items:
> > +      - const: source
> > +      - const: hclk
> > +      - const: source_cg
> > +      - const: bus_clk
> > +
> > +  pinctrl-names:
> > +    items:
> > +      - const: default
> > +      - const: state_uhs
> > +
> > +  pinctrl-0:
> > +    description:
> > +      should contain default/high speed pin ctrl.
> > +    maxItems: 1
> > +
> > +  pinctrl-1:
> > +    description:
> > +      should contain uhs mode pin ctrl.
> > +    maxItems: 1
> > +
> > +  vmmc-supply:
> > +    description:
> > +      power to the Core.
> > +
> > +  vqmmc-supply:
> > +    description:
> > +      power to the IO.
> > +
> > +  assigned-clocks:
> > +    description:
> > +      PLL of the source clock.
> 
> How many (maxItems)?
> 
> > +
> > +  assigned-clock-parents:
> > +    description:
> > +      parent of source clock, used for HS400 mode to get 400Mhz source clock.
> > +
> > +  hs400-ds-delay:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      HS400 DS delay setting.
> > +
> > +  mediatek,hs200-cmd-int-delay:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      HS200 command internal delay setting.
> > +      This field has total 32 stages.
> > +      The value is an integer from 0 to 31.
> 
> minimum: 0
> maximum: 31
> 
> Add any constraints on other properties too.
> 
> > +
> > +  mediatek,hs400-cmd-int-delay:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      HS400 command internal delay setting.
> > +      This field has total 32 stages.
> > +      The value is an integer from 0 to 31.
> > +
> > +  mediatek,hs400-cmd-resp-sel-rising:
> > +    $ref: /schemas/types.yaml#/definitions/flag
> > +    description:
> > +      HS400 command response sample selection.
> > +      If present, HS400 command responses are sampled on rising edges.
> > +      If not present, HS400 command responses are sampled on falling edges.
> > +
> > +  mediatek,latch-ck:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +    description:
> > +      Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
> > +      data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
> > +      if not present, default value is 0.
> > +      applied to compatible "mediatek,mt2701-mmc".
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +  reset-names:
> > +    const: hrst
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/clock/mt8173-clk.h>
> > +    mmc0: mmc@11230000 {
> > +        compatible = "mediatek,mt8173-mmc";
> > +        reg = <0x11230000 0x1000>;
> > +        interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
> > +        vmmc-supply = <&mt6397_vemc_3v3_reg>;
> > +        vqmmc-supply = <&mt6397_vio18_reg>;
> > +        clocks = <&pericfg CLK_PERI_MSDC30_0>,
> > +                 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
> > +        clock-names = "source", "hclk";
> > +        pinctrl-names = "default", "state_uhs";
> > +        pinctrl-0 = <&mmc0_pins_default>;
> > +        pinctrl-1 = <&mmc0_pins_uhs>;
> > +        assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
> > +        assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
> > +        hs400-ds-delay = <0x14015>;
> > +        mediatek,hs200-cmd-int-delay = <26>;
> > +        mediatek,hs400-cmd-int-delay = <14>;
> > +        mediatek,hs400-cmd-resp-sel-rising;
> > +    };
> > +
> > +...
> > -- 
> > 2.18.0