Re: [RESEND PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips

[Vignesh Raghavendra]

Hi,

On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
> 
> Tested with mx25l51245g(BP0-3).

Since you have only tested on flash that have 4bit BP, please don't
modify flashes that have 3bit BP. Lets be conservative and enable only
things that have been tested else we may end up with broken feature from
day 1.

Regards
Vignesh

> 
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@xxxxxxxxx>
> ---
>  drivers/mtd/spi-nor/macronix.c | 75 ++++++++++++++++++++++------------
>  1 file changed, 50 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 96735d83c77c..80de43eb05d6 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -37,53 +37,78 @@ static const struct flash_info macronix_parts[] = {
>  	/* Macronix */
>  	{ "mx25l512e",   INFO(0xc22010, 0, 64 * 1024,   1, SECT_4K) },
>  	{ "mx25l2005a",  INFO(0xc22012, 0, 64 * 1024,   4, SECT_4K) },
> -	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8, SECT_4K) },
> -	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16, 0) },
> -	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32, SECT_4K) },
> -	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64, SECT_4K) },
> -	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64, SECT_4K) },
> -	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
> -	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4, SECT_4K) },
> +	{ "mx25l4005a",  INFO(0xc22013, 0, 64 * 1024,   8,
> +			      SECT_4K | SPI_NOR_HAS_LOCK) },
> +	{ "mx25l8005",   INFO(0xc22014, 0, 64 * 1024,  16,
> +			      SPI_NOR_HAS_LOCK) },
> +	{ "mx25l1606e",  INFO(0xc22015, 0, 64 * 1024,  32,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25l3205d",  INFO(0xc22016, 0, 64 * 1024,  64,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25l3255e",  INFO(0xc29e16, 0, 64 * 1024,  64,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25l6405d",  INFO(0xc22017, 0, 64 * 1024, 128,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25u2033e",  INFO(0xc22532, 0, 64 * 1024,   4,
> +			      SECT_4K | SPI_NOR_HAS_LOCK) },
>  	{ "mx25u3235f",	 INFO(0xc22536, 0, 64 * 1024,  64,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ) },
> -	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8, SECT_4K) },
> -	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16, SECT_4K) },
> -	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
> -	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
> -	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
> +	{ "mx25u4035",   INFO(0xc22533, 0, 64 * 1024,   8,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25u8035",   INFO(0xc22534, 0, 64 * 1024,  16,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25u6435f",  INFO(0xc22537, 0, 64 * 1024, 128,
> +			      SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256,
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> +	{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256,
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
>  	{ "mx25r3235f",  INFO(0xc22816, 0, 64 * 1024,  64,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
> -			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> +			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP)
>  		.fixups = &mx25l25635_fixups },
>  	{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
> -			      SECT_4K | SPI_NOR_4B_OPCODES) },
> +			      SECT_4K | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
>  	{ "mx25v8035f",  INFO(0xc22314, 0, 64 * 1024,  16,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ) },
> -	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
> +	{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512,
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
>  	{ "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
>  			      SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> -			      SPI_NOR_4B_OPCODES) },
> +			      SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
>  			      SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> -			      SPI_NOR_4B_OPCODES) },
> +			      SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> +			      SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
>  	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048,
>  			      SECT_4K | SPI_NOR_DUAL_READ |
> -			      SPI_NOR_QUAD_READ) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
> -			      SPI_NOR_QUAD_READ) },
> +			      SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> +			      SPI_NOR_4BIT_BP) },
>  };
>  
>  static void macronix_default_init(struct spi_nor *nor)
>