Re: [PATCH v2 4/5] PCI: qcom: Add SM8250 SoC support

From: Manivannan Sadhasivam
Date: Thu Oct 01 2020 - 01:35:00 EST


Hi Stan,

On Thu, Oct 01, 2020 at 12:56:28AM +0300, Stanimir Varbanov wrote:
> Hi Mani,
>
> On 9/30/20 6:09 PM, Manivannan Sadhasivam wrote:
> > The PCIe IP on SM8250 SoC is similar to the one used on SDM845. Hence
> > the support is added reusing the members of ops_2_7_0. The key
> > difference between ops_2_7_0 and ops_sm8250 is the config_sid callback,
> > which will be added in successive commit.
> >
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> > ---
> > drivers/pci/controller/dwc/pcie-qcom.c | 11 +++++++++++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> > index 3aac77a295ba..44db91861b47 100644
> > --- a/drivers/pci/controller/dwc/pcie-qcom.c
> > +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> > @@ -1359,6 +1359,16 @@ static const struct qcom_pcie_ops ops_2_7_0 = {
> > .post_deinit = qcom_pcie_post_deinit_2_7_0,
> > };
> >
> > +/* Qcom IP rev.: 1.9.0 */
> > +static const struct qcom_pcie_ops ops_sm8250 = {
>
> This breaks the policy compatible -> ops_X_Y_Z. Could you introduce new
> method config_sid and check into for compatible qcom,pcie-sm8250 string
> there?
>

I thought about it but during previous submission review Bjorn mentioned that
this config_sid got introduced in SM8150 and there might be chances that future
SoCs could also use it. That's why I was inclined to introduce a new ops instead
of checking for the compatible.

And the reason to use "sm8250" instead of IP revision is that I can't find the
Synopsys IP revision for this. But if you strongly prefer IP revision then I can
just use "ops_1_9_0"!

Thanks,
Mani

> > + .get_resources = qcom_pcie_get_resources_2_7_0,
> > + .init = qcom_pcie_init_2_7_0,
> > + .deinit = qcom_pcie_deinit_2_7_0,
> > + .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
> > + .post_init = qcom_pcie_post_init_2_7_0,
> > + .post_deinit = qcom_pcie_post_deinit_2_7_0,
> > +};
> > +
> > static const struct dw_pcie_ops dw_pcie_ops = {
> > .link_up = qcom_pcie_link_up,
> > };
> > @@ -1476,6 +1486,7 @@ static const struct of_device_id qcom_pcie_match[] = {
> > { .compatible = "qcom,pcie-ipq4019", .data = &ops_2_4_0 },
> > { .compatible = "qcom,pcie-qcs404", .data = &ops_2_4_0 },
> > { .compatible = "qcom,pcie-sdm845", .data = &ops_2_7_0 },
> > + { .compatible = "qcom,pcie-sm8250", .data = &ops_sm8250 },
> > { }
> > };
> >
> >
>
> --
> regards,
> Stan