Re: PHY reset question

[Marco Felsch]

On 20-10-07 10:23, Marek Vasut wrote:
> On 10/7/20 10:14 AM, Marco Felsch wrote:
> > Hi Marek,
> 
> Hi,
> 
> [...]
> 
> > On 20-10-06 14:11, Florian Fainelli wrote:
> >> On 10/6/2020 1:24 PM, Marek Vasut wrote:
> > 
> > ...
> > 
> >>> If this happens on MX6 with FEC, can you please try these two patches?
> >>>
> >>> https://patchwork.ozlabs.org/project/netdev/patch/20201006135253.97395-1-marex@xxxxxxx/
> >>>
> >>> https://patchwork.ozlabs.org/project/netdev/patch/20201006202029.254212-1-marex@xxxxxxx/
> >>
> >> Your patches are not scaling across multiple Ethernet MAC drivers
> >> unfortunately, so I am not sure this should be even remotely considered a
> >> viable solution.
> > 
> > Recently I added clk support for the smcs driver [1] and dropped the
> > PHY_RST_AFTER_CLK_EN flag for LAN8710/20 devices because I had the same
> > issues. Hope this will help you too.
> > 
> > [1] https://www.spinics.net/lists/netdev/msg682080.html
> 
> I feel this might be starting to go a bit off-topic here,

You're right, just wanted to provide you a link :)

> but isn't the
> last patch 5/5 breaking existing setups ?

IMHO the solution proposed using the PHY_RST_AFTER_CLK_EN was wrong so
we needed to fix that. Yes we need to take care of DT backward
compatibility but we still must be able to fix wrong behaviours within
the driver. I could also argue that PHY_RST_AFTER_CLK_EN solution was
breaking exisitng setups too.

> The LAN8710 surely does need
> clock enabled before the reset line is toggled.

Yep and therefore you can specify it yet within the DT.

Regards,
  Marco