Re: [PATCH 3/5] clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL
From: Stephen Boyd
Date: Tue Oct 13 2020 - 23:06:30 EST
Quoting Paul Cercueil (2020-09-02 18:50:46)
> CLK_SET_RATE_GATE means that the clock must be gated when being
> reclocked. This is not the case for the PLLs in Ingenic SoCs.
>
> Signed-off-by: Paul Cercueil <paul@xxxxxxxxxxxxxxx>
> ---
Applied to clk-next