Re: [PATCH RFC v4 06/13] perf vendor events arm64: Add hip09 SMMUv3 PMCG events
From: Robin Murphy
Date: Wed Oct 14 2020 - 14:06:53 EST
On 2020-10-08 11:15, John Garry wrote:
Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip09
platform.
This contains a mix of architected and IMP def events
Signed-off-by: John Garry <john.garry@xxxxxxxxxx>
---
.../hisilicon/hip09/sys/smmu-v3-pmcg.json | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
new file mode 100644
index 000000000000..8abafbb2dcb4
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip09/sys/smmu-v3-pmcg.json
@@ -0,0 +1,42 @@
+[
+ {
+ "ArchStdEvent": "smmuv3_pmcg.CYCLES"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.TRANSACTION"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.TLB_MISS"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ"
+ "Compat": "0x00030736"
+ },
+ {
+ "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED"
+ "Compat": "0x00030736"
+ },
+ {
+ "EventCode": "0x8a",
+ "EventName": "smmuv3_pmcg.L1_TLB",
+ "BriefDescription": "SMMUv3 PMCG L1 TABLE transation",
+ "PublicDescription": "SMMUv3 PMCG L1 TABLE transation",
Those typos are either missing "c"s or "l"s, but with SMMU it's never
clear which ;)
Robin.
+ "Unit": "smmuv3_pmcg",
+ "Compat": "0x00030736"
+ },
+]