Re: [PATCH] clk: imx8mq: Fix usdhc parents order

[Fabio Estevam]

Hi Abel,

On Thu, Oct 15, 2020 at 6:26 AM Abel Vesa <abel.vesa@xxxxxxx> wrote:
>
> According to the latest RM (see Table 5-1. Clock Root Table),
> both usdhc root clocks have the parent order as follows:
>
> 000 - 25M_REF_CLK
> 001 - SYSTEM_PLL1_DIV2
> 010 - SYSTEM_PLL1_CLK
> 011 - SYSTEM_PLL2_DIV2
> 100 - SYSTEM_PLL3_CLK
> 101 - SYSTEM_PLL1_DIV3
> 110 - AUDIO_PLL2_CLK
> 111 - SYSTEM_PLL1_DIV8
>
> So the audio_pll2_out and sys3_pll_out have to be swapped.
>
> Fixes: b80522040cd3 ("clk: imx: Add clock driver for i.MX8MQ CCM")
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxx>
> Reported-by: Cosmin Stefan Stoica <cosmin.stoica@xxxxxxx>

Thanks for the fix:

Reviewed-by: Fabio Estevam <festevam@xxxxxxxxx>