Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance

From: Daniel Vetter
Date: Thu Oct 15 2020 - 11:33:41 EST


On Thu, Oct 15, 2020 at 07:55:32AM +0100, Christoph Hellwig wrote:
> On Tue, Oct 13, 2020 at 02:42:38PM +0100, Robin Murphy wrote:
> > I still think this situation would be best handled with a variant of
> > dma_ops_bypass that also guarantees to bypass SWIOTLB, and can be set
> > automatically when attaching to an unmanaged IOMMU domain.
>
> dma_ops_bypass should mostly do the right thing as-is. swiotlb bouncing
> is triggered of two things:
>
> 1) the dma_mask. This is under control of the driver, and obviously
> if it is too small for a legit reason we can't just proceed

Somewhat related, but is there a way to tell the dma-api to fail instead
of falling back to swiotlb? In many case for gpu drivers it's much better
if we fall back to dma_alloc_coherent and manage the copying ourselves
instead of abstracting this away in the dma-api. Currently that's "solved"
rather pessimistically by always allocating from dma_alloc_coherent if
swiotlb could be in the picture (at least for ttm based drivers, i915 just
falls over).
-Daniel

> 2) force_dma_unencrypted() - we'd need to do an opt-out here, either
> by a flag or by being smart and looking for an attached iommu on
> the device
>
> > That way the
> > device driver can make DMA API calls in the appropriate places that do the
> > right thing either way, and only needs logic to decide whether to use the
> > returned DMA addresses directly or ignore them if it knows they're
> > overridden by its own IOMMU mapping.
>
> I'd be happy to review patches for this.

--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch