[PATCH v4 18/34] clk: mediatek: Add MT8192 imgsys2 clock support

[Weiyi Lu]

Add MT8192 imgsys2 clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
---
 drivers/clk/mediatek/Kconfig           |  6 ++++
 drivers/clk/mediatek/Makefile          |  1 +
 drivers/clk/mediatek/clk-mt8192-img2.c | 62 ++++++++++++++++++++++++++++++++++
 3 files changed, 69 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8192-img2.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index afd028b..99b0168 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -485,6 +485,12 @@ config COMMON_CLK_MT8192_IMGSYS
 	help
 	  This driver supports MediaTek MT8192 imgsys clocks.
 
+config COMMON_CLK_MT8192_IMGSYS2
+	bool "Clock driver for MediaTek MT8192 imgsys2"
+	depends on COMMON_CLK_MT8192
+	help
+	  This driver supports MediaTek MT8192 imgsys2 clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 1f87bec..012a01a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -68,5 +68,6 @@ obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWA) += clk-mt8192-cam_rawa.o
 obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWB) += clk-mt8192-cam_rawb.o
 obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS_RAWC) += clk-mt8192-cam_rawc.o
 obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS) += clk-mt8192-img.o
+obj-$(CONFIG_COMMON_CLK_MT8192_IMGSYS2) += clk-mt8192-img2.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8192-img2.c b/drivers/clk/mediatek/clk-mt8192-img2.c
new file mode 100644
index 0000000..76f9e32
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8192-img2.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Author: Weiyi Lu <weiyi.lu@xxxxxxxxxxxx>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8192-clk.h>
+
+static const struct mtk_gate_regs img2_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_IMG2(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &img2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate img2_clks[] = {
+	GATE_IMG2(CLK_IMG2_LARB11, "img2_larb11", "img1_sel", 0),
+	GATE_IMG2(CLK_IMG2_LARB12, "img2_larb12", "img1_sel", 1),
+	GATE_IMG2(CLK_IMG2_MFB, "img2_mfb", "img1_sel", 6),
+	GATE_IMG2(CLK_IMG2_WPE, "img2_wpe", "img1_sel", 7),
+	GATE_IMG2(CLK_IMG2_MSS, "img2_mss", "img1_sel", 8),
+	GATE_IMG2(CLK_IMG2_GALS, "img2_gals", "img1_sel", 12),
+};
+
+static int clk_mt8192_img2_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_IMG2_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, img2_clks, ARRAY_SIZE(img2_clks), clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8192_img2[] = {
+	{ .compatible = "mediatek,mt8192-imgsys2", },
+	{}
+};
+
+static struct platform_driver clk_mt8192_img2_drv = {
+	.probe = clk_mt8192_img2_probe,
+	.driver = {
+		.name = "clk-mt8192-img2",
+		.of_match_table = of_match_clk_mt8192_img2,
+	},
+};
+
+builtin_platform_driver(clk_mt8192_img2_drv);
-- 
1.8.1.1.dirty