Re: [PATCH v2 2/7] ASoC: audio-graph-card: Add plls and sysclks DT bindings

[Mark Brown]

On Mon, Oct 26, 2020 at 08:27:04AM -0500, Rob Herring wrote:
> On Fri, Oct 16, 2020 at 06:35:36PM +0100, Richard Fitzgerald wrote:

> > +- plls: A list of component pll settings that will be applied with
> > +      snd_soc_component_set_pll. Each entry is a phandle to the node of the
> > +      codec or cpu component, followed by the four arguments id, source,
> > +      frequency_in, frequency_out. Multiple entries can have the same phandle
> > +      so that several plls can be set in the same component.

> Where do the values of id and source come from?

The device bindings will need to define them.

> > +- sysclks: A list of component sysclk settings that will be applied with
> > +      snd_soc_component_set_sysclk. Each entry is a phandle to the node of
> > +      the codec or cpu component, followed by the four arguments id, source,
> > +      frequency, direction. Direction is 0 if the clock is an input, 1 if it
> > +      is an output. Multiple entries can have the same phandle so that several
> > +      clocks can be set in the same component.

> Are these really common properties? They seem kind of Cirrus specific 
> and perhaps should be located in the codec node(s).

It's very common for audio devices to have very flexible clocking, to
the exetent this is Linux specific it's issues with the clock API not
being able to handle clock controllers on buses that need clock control
to access rather than conceptually.

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