Re: [PATCH 1/5] memory: tegra: Correct la.reg address of seswr

[Krzysztof Kozlowski]

On Wed, Oct 07, 2020 at 05:37:42PM -0700, Nicolin Chen wrote:
> According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field
> [23:16] of register at address 0x3e0 with a reset value of 0x80
> at register 0x3e0, while bit-1 of register 0xb98 is for enable
> bit of seswr.

> So this patch fixes it.

Either use the imperative form ("Fix foo bar register address") or just
skip the last sentence as it is quite obvious.

https://elixir.bootlin.com/linux/latest/source/Documentation/process/submitting-patches.rst#L151

Thanks, applied.

Best regards,
Krzysztof