On Fri, Oct 16, 2020 at 06:35:36PM +0100, Richard Fitzgerald wrote:
This adds the two new properties 'plls' and 'sysclks' to the dt bindings.
These add the ability to set values that will be
passed to snd_soc_component_set_sysclk() and snd_soc_component_set_pll().
I worry this looks like Linux implementation details leaking into the
binding.
Signed-off-by: Richard Fitzgerald <rf@xxxxxxxxxxxxxxxxxxxxx>
---
.../bindings/sound/audio-graph-card.txt | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/audio-graph-card.txt b/Documentation/devicetree/bindings/sound/audio-graph-card.txt
index d5f6919a2d69..59bbd5b55b59 100644
--- a/Documentation/devicetree/bindings/sound/audio-graph-card.txt
+++ b/Documentation/devicetree/bindings/sound/audio-graph-card.txt
@@ -32,6 +32,19 @@ Required properties:
Optional properties:
- pa-gpios: GPIO used to control external amplifier.
+- plls: A list of component pll settings that will be applied with
+ snd_soc_component_set_pll. Each entry is a phandle to the node of the
+ codec or cpu component, followed by the four arguments id, source,
+ frequency_in, frequency_out. Multiple entries can have the same phandle
+ so that several plls can be set in the same component.
Where do the values of id and source come from?
+
+- sysclks: A list of component sysclk settings that will be applied with
+ snd_soc_component_set_sysclk. Each entry is a phandle to the node of
+ the codec or cpu component, followed by the four arguments id, source,
+ frequency, direction. Direction is 0 if the clock is an input, 1 if it
+ is an output. Multiple entries can have the same phandle so that several
+ clocks can be set in the same component.
Are these really common properties? They seem kind of Cirrus specific
and perhaps should be located in the codec node(s).
+
-----------------------
Example: Single DAI case
-----------------------
@@ -335,3 +348,34 @@ Example: Multi DAI with DPCM
};
};
};
+
+-----------------------
+Example: Set component sysclks and PLLs
+-----------------------
+
+ sound {
+ compatible = "audio-graph-card";
+
+ sysclks = <
+ &cs47l15 1 4 98304000 0
+ &cs47l15 8 4 147456000 0
+ >;
+ plls = <
+ &cs47l15 1 0 24576000 98304000
+ >;
+
+ dais = <&cpu_i2s_port>;
+ };
+
+ cs47l15: codec@0 {
+ ...
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs47l15_aif1_port: port@0 {
+ reg = <0>;
+ cs47l15_aif1: endpoint {
+ remote-endpoint = <&cpu_i2s_endpoint>;
+ };
+ };
+ };
--
2.20.1