Re: [PATCH v1 3/4] phy: Add Sparx5 ethernet serdes PHY driver

From: kernel test robot
Date: Tue Nov 10 2020 - 06:04:25 EST

Next message: Tony Lindgren: "[PATCH] soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted"
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Hi Steen,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master phy/next linux/master v5.10-rc3 next-20201110]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201105-224623
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: h8300-randconfig-r023-20201109 (attached as .config)
compiler: h8300-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/cf09fd205f64b7c78c3078d3888f54baccf102e4
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Steen-Hegelund/Adding-the-Sparx5-Serdes-driver/20201105-224623
git checkout cf09fd205f64b7c78c3078d3888f54baccf102e4
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=h8300

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

In file included from include/linux/init.h:5,
from include/linux/printk.h:6,
from drivers/phy/microchip/sparx5_serdes.c:9:
include/linux/scatterlist.h: In function 'sg_set_buf':
include/asm-generic/page.h:93:50: warning: ordered comparison of pointer with null pointer [-Wextra]
93 | #define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
| ^~
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
78 | # define unlikely(x) __builtin_expect(!!(x), 0)
| ^
include/linux/scatterlist.h:143:2: note: in expansion of macro 'BUG_ON'
143 | BUG_ON(!virt_addr_valid(buf));
| ^~~~~~
include/linux/scatterlist.h:143:10: note: in expansion of macro 'virt_addr_valid'
143 | BUG_ON(!virt_addr_valid(buf));
| ^~~~~~~~~~~~~~~
drivers/phy/microchip/sparx5_serdes.c: In function 'sparx5_sd25g28_get_params':
>> drivers/phy/microchip/sparx5_serdes.c:821:33: warning: initialized field overwritten [-Woverride-init]
821 | .cfg_rx_reserve_15_8 = 0x61,
| ^~~~
drivers/phy/microchip/sparx5_serdes.c:821:33: note: (near initialization for 'init.cfg_rx_reserve_15_8')
drivers/phy/microchip/sparx5_serdes.c:828:33: warning: initialized field overwritten [-Woverride-init]
828 | .cfg_pi_en = 1,
| ^
drivers/phy/microchip/sparx5_serdes.c:828:33: note: (near initialization for 'init.cfg_pi_en')
drivers/phy/microchip/sparx5_serdes.c:843:33: warning: initialized field overwritten [-Woverride-init]
843 | .cfg_cdrck_en = 1,
| ^
drivers/phy/microchip/sparx5_serdes.c:843:33: note: (near initialization for 'init.cfg_cdrck_en')
drivers/phy/microchip/sparx5_serdes.c: In function 'sparx5_sd10g28_get_params':
drivers/phy/microchip/sparx5_serdes.c:949:34: warning: initialized field overwritten [-Woverride-init]
949 | .cfg_cdrck_en = 1,
| ^
drivers/phy/microchip/sparx5_serdes.c:949:34: note: (near initialization for 'init.cfg_cdrck_en')

vim +821 drivers/phy/microchip/sparx5_serdes.c

738
739 static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,
740 struct sparx5_sd25g28_media_preset *media,
741 struct sparx5_sd25g28_mode_preset *mode,
742 struct sparx5_sd25g28_args *args,
743 struct sparx5_sd25g28_params *params)
744 {
745 struct sparx5_sd25g28_params init = {
746 .r_d_width_ctrl_2_0 = sd25g28_get_iw_setting(mode->bitwidth),
747 .r_txfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
748 .r_rxfifo_ck_div_pmad_2_0 = mode->fifo_ck_div,
749 .cfg_vco_div_mode_1_0 = mode->vco_div_mode,
750 .cfg_pre_divsel_1_0 = mode->pre_divsel,
751 .cfg_sel_div_3_0 = mode->sel_div,
752 .cfg_vco_start_code_3_0 = 0,
753 .cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,
754 .cfg_tx_prediv_1_0 = mode->tx_pre_div,
755 .cfg_rxdiv_sel_2_0 = mode->ck_bitwidth,
756 .cfg_tx_subrate_2_0 = mode->subrate,
757 .cfg_rx_subrate_2_0 = mode->subrate,
758 .r_multi_lane_mode = 0,
759 .cfg_cdrck_en = 1,
760 .cfg_dfeck_en = mode->dfe_enable,
761 .cfg_dfe_pd = mode->dfe_enable == 1 ? 0 : 1,
762 .cfg_dfedmx_pd = 1,
763 .cfg_dfetap_en_5_1 = mode->dfe_tap,
764 .cfg_dmux_pd = 0,
765 .cfg_dmux_clk_pd = 1,
766 .cfg_erramp_pd = mode->dfe_enable == 1 ? 0 : 1,
767 .cfg_pi_DFE_en = mode->dfe_enable,
768 .cfg_pi_en = 1,
769 .cfg_pd_ctle = 0,
770 .cfg_summer_en = 1,
771 .cfg_pmad_ck_pd = 0,
772 .cfg_pd_clk = 0,
773 .cfg_pd_cml = 0,
774 .cfg_pd_driver = 0,
775 .cfg_rx_reg_pu = 1,
776 .cfg_pd_rms_det = 1,
777 .cfg_dcdr_pd = 0,
778 .cfg_ecdr_pd = 1,
779 .cfg_pd_sq = 1,
780 .cfg_itx_ipdriver_base_2_0 = mode->txmargin,
781 .cfg_tap_dly_4_0 = media->cfg_tap_dly_4_0,
782 .cfg_tap_main = media->cfg_tap_main,
783 .cfg_en_main = media->cfg_en_main,
784 .cfg_tap_adv_3_0 = media->cfg_tap_adv_3_0,
785 .cfg_en_adv = media->cfg_en_adv,
786 .cfg_en_dly = media->cfg_en_dly,
787 .cfg_iscan_en = 0,
788 .l1_pcs_en_fast_iscan = 0,
789 .l0_cfg_bw_1_0 = 0,
790 .cfg_en_dummy = 0,
791 .cfg_pll_reserve_3_0 = args->com_pll_reserve,
792 .l0_cfg_txcal_en = mode->com_txcal_en,
793 .l0_cfg_tx_reserve_15_8 = mode->com_tx_reserve_msb,
794 .l0_cfg_tx_reserve_7_0 = mode->com_tx_reserve_lsb,
795 .cfg_tx_reserve_15_8 = mode->tx_reserve_msb,
796 .cfg_tx_reserve_7_0 = mode->tx_reserve_lsb,
797 .cfg_bw_1_0 = mode->bw,
798 .cfg_txcal_man_en = 1,
799 .cfg_phase_man_4_0 = 0,
800 .cfg_quad_man_1_0 = 0,
801 .cfg_txcal_shift_code_5_0 = 2,
802 .cfg_txcal_valid_sel_3_0 = 4,
803 .cfg_txcal_en = 0,
804 .cfg_cdr_kf_2_0 = 1,
805 .cfg_cdr_m_7_0 = 6,
806 .cfg_pi_bw_3_0 = mode->cfg_pi_bw_3_0,
807 .cfg_pi_steps_1_0 = 0,
808 .cfg_dis_2ndorder = 1,
809 .cfg_ctle_rstn = mode->cfg_ctle_rstn,
810 .r_dfe_rstn = mode->r_dfe_rstn,
811 .cfg_alos_thr_2_0 = media->cfg_alos_thr_2_0,
812 .cfg_itx_ipcml_base_1_0 = mode->cfg_itx_ipcml_base,
813 .cfg_rx_reserve_7_0 = 0xbf,
814 .cfg_rx_reserve_15_8 = 0x61,
815 .cfg_rxterm_2_0 = mode->rxterm,
816 .cfg_fom_selm = 0,
817 .cfg_rx_sp_ctle_1_0 = 0,
818 .cfg_isel_ctle_1_0 = 0,
819 .cfg_vga_ctrl_byp_4_0 = media->cfg_vga_ctrl_byp_4_0,
820 .cfg_vga_byp = 1,
> 821 .cfg_rx_reserve_15_8 = 0x61,
822 .cfg_agc_adpt_byp = 1,
823 .cfg_eqr_byp = 1,
824 .cfg_eqr_force_3_0 = media->cfg_eq_r_force_3_0,
825 .cfg_eqc_force_3_0 = media->cfg_eq_c_force_3_0,
826 .cfg_sum_setcm_en = 1,
827 .cfg_pi_dfe_en = 1,
828 .cfg_pi_en = 1,
829 .cfg_init_pos_iscan_6_0 = 6,
830 .cfg_init_pos_ipi_6_0 = 9,
831 .cfg_dfedig_m_2_0 = 6,
832 .cfg_en_dfedig = mode->dfe_enable,
833 .r_d_width_ctrl_from_hwt = 0,
834 .r_reg_manual = 1,
835 .reg_rst = args->reg_rst,
836 .cfg_jc_byp = 1,
837 .cfg_common_reserve_7_0 = 1,
838 .cfg_pll_lol_set = 1,
839 .cfg_tx2rx_lp_en = 0,
840 .cfg_txlb_en = 0,
841 .cfg_rx2tx_lp_en = 0,
842 .cfg_rxlb_en = 0,
843 .cfg_cdrck_en = 1,
844 .r_tx_pol_inv = args->txinvert,
845 .r_rx_pol_inv = args->rxinvert,
846 };
847
848 *params = init;
849 }
850

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip

Next message: Tony Lindgren: "[PATCH] soc: ti: omap-prm: Do not check rstst bit on deassert if already deasserted"
Previous message: Vikas Gupta: "Re: [RFC, v0 1/3] vfio/platform: add support for msi"
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