Re: [EXTERNAL] [tip: x86/apic] x86/io_apic: Cleanup trigger/polarity helpers

[David Woodhouse]

On 10 November 2020 21:01:17 GMT, Thomas Gleixner <tglx@xxxxxxxxxxxxx> wrote:
>On Tue, Nov 10 2020 at 19:21, David Woodhouse wrote:
>
>> On 10 November 2020 18:56:17 GMT, Thomas Gleixner
><tglx@xxxxxxxxxxxxx> wrote:
>>>On Tue, Nov 10 2020 at 18:50, Thomas Gleixner wrote:
>>>> On Tue, Nov 10 2020 at 16:33, David Woodhouse wrote:
>>>>> If I could get post-5.5 kernels to boot at all with the AMD IOMMU
>>>>> enabled, I'd have a go at throwing that together now...
>>>>
>>>> It can share the dmar domain code. Let me frob something.
>>>
>>>Not much to share there and I can't access my AMD machine at the
>>>moment. Something like the untested below should work.
>>
>> Does it even need its own irqdomain? Can it not just allocate
>directly
>> from the vector domain then program its own register directly based
>on
>> the irq_cfg?
>
>It uses pci_enable_msi() and I have no clue about that piece of
>hardware
>and whether that is actually required or not. If it is, then it needs a
>domain because that's what pci_enable_msi() uses.

I'd be kind of surprised if it is required, but testing on qemu is obviously not going to cut it. Tom?

-- 
Sent from my Android device with K-9 Mail. Please excuse my brevity.