[PATCH 1/2] dt-bindings: hwlock: add sunxi hwlock

[fuyao]

From: fuyao <fuyao@xxxxxxxxxxxxxxxxx>

SUNXI hwspinlock binding DT schema format

Signed-off-by: fuyao <fuyao@xxxxxxxxxxxxxxxxx>
---
 .../bindings/hwlock/sunxi,hwspinlock.yaml     | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/hwlock/sunxi,hwspinlock.yaml

diff --git a/Documentation/devicetree/bindings/hwlock/sunxi,hwspinlock.yaml b/Documentation/devicetree/bindings/hwlock/sunxi,hwspinlock.yaml
new file mode 100644
index 0000000000000..68ce93b6d2bcb
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwlock/sunxi,hwspinlock.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwlock/sunxi,hwspinlock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SUNXI HwSpinlock for SUNXI
+
+maintainers:
+  - fuyao <fuyao@xxxxxxxxxxxxxxxxx>
+
+properties:
+  compatible:
+    enum:
+      - allwinner,h3-hwspinlock,  # for h3-hwspinlock
+      - allwinner,h6-hwspinlock,  # for h6-hwspinlock
+
+  reg:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+
+  - |
+    hwspinlock: spinlock@1c17000 {
+        compatible = "allwinner,h3-hwspinlock";
+        reg = <0x0 0x01c17000 0x0 0x1000>;
+        clocks = <&ccu CLK_BUS_SPINLOCK>;
+        resets = <&ccu RST_BUS_SPINLOCK>;
+    };
+
+  - |
+    hwspinlock: spinlock@3004000 {
+        compatible = "allwinner,h6-hwspinlock";
+        reg = <0x0 0x03004000 0x0 0x1000>;
+        clocks = <&ccu CLK_BUS_SPINLOCK>;
+        resets = <&ccu RST_BUS_SPINLOCK>;
+    };
+
-- 
2.29.2