Re: [PATCH v1 3/7] spi: qspi-tegra: Add support for Tegra210 QSPI controller

From: kernel test robot
Date: Tue Dec 01 2020 - 19:10:53 EST

Hi Sowjanya,

I love your patch! Perhaps something to improve:

[auto build test WARNING on spi/for-next]
[also build test WARNING on robh/for-next tegra/for-next v5.10-rc6 next-20201201]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Sowjanya-Komatineni/Add-Tegra-QSPI-driver/20201202-051629
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
config: riscv-allyesconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/a8da475b681c83105cdb8daf7408cc92aca9f65a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sowjanya-Komatineni/Add-Tegra-QSPI-driver/20201202-051629
git checkout a8da475b681c83105cdb8daf7408cc92aca9f65a
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

drivers/spi/qspi-tegra.c: In function 'tegra_qspi_transfer_one_message':
>> drivers/spi/qspi-tegra.c:935:7: warning: variable 'skip' set but not used [-Wunused-but-set-variable]
935 | bool skip = false;
| ^~~~

vim +/skip +935 drivers/spi/qspi-tegra.c

925
926 static int tegra_qspi_transfer_one_message(struct spi_master *master,
927 struct spi_message *msg)
928 {
929 bool is_first_msg = true;
930 struct tegra_qspi_data *tqspi = spi_master_get_devdata(master);
931 struct spi_transfer *xfer;
932 struct spi_device *spi = msg->spi;
933 u8 dummy_cycles, ntransfers = 0;
934 int ret;
> 935 bool skip = false;
936 int xfer_phase = 0;
937
938 msg->status = 0;
939 msg->actual_length = 0;
940 tqspi->tx_status = 0;
941 tqspi->rx_status = 0;
942
943 /*
944 * Tegra QSPI hardware support dummy bytes transfer based on the
945 * programmed dummy clock cyles in QSPI register.
946 * So, get the total dummy bytes from the dummy bytes transfer in
947 * spi_messages and convert to dummy clock cyles.
948 */
949 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
950 if (ntransfers == DUMMY_BYTES_XFER &&
951 !(list_is_last(&xfer->transfer_list, &msg->transfers)))
952 dummy_cycles = xfer->len * 8 / xfer->tx_nbits;
953 ntransfers++;
954 }
955
956 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
957 u32 cmd1;
958
959 /*
960 * Program dummy clock cycles in Tegra QSPI register only
961 * during address transfer phase.
962 */
963 if (xfer_phase == ADDR_BYTES_XFER)
964 tqspi->dummy_cycles = dummy_cycles;
965 else
966 tqspi->dummy_cycles = 0;
967
968 /*
969 * Tegra QSPI hardware support dummy bytes transfer.
970 * So, skip the transfer of dummy bytes from the software.
971 */
972 if (ntransfers == MAX_XFERS &&
973 xfer_phase == DUMMY_BYTES_XFER) {
974 msg->actual_length += xfer->len;
975 xfer_phase++;
976 continue;
977 }
978
979 reinit_completion(&tqspi->xfer_completion);
980
981 cmd1 = tegra_qspi_setup_transfer_one(spi, xfer, is_first_msg);
982 if (!xfer->len) {
983 ret = 0;
984 skip = true;
985 goto exit;
986 }
987
988 ret = tegra_qspi_start_transfer_one(spi, xfer, cmd1);
989 if (ret < 0) {
990 dev_err(tqspi->dev,
991 "failed to start transfer: %d\n", ret);
992 goto exit;
993 }
994
995 is_first_msg = false;
996 ret = wait_for_completion_timeout(&tqspi->xfer_completion,
997 QSPI_DMA_TIMEOUT);
998 if (WARN_ON(ret == 0)) {
999 dev_err(tqspi->dev,
1000 "qspi transfer timeout: %d\n", ret);
1001 if (tqspi->is_curr_dma_xfer &&
1002 (tqspi->cur_direction & DATA_DIR_TX))
1003 dmaengine_terminate_all(tqspi->tx_dma_chan);
1004 if (tqspi->is_curr_dma_xfer &&
1005 (tqspi->cur_direction & DATA_DIR_RX))
1006 dmaengine_terminate_all(tqspi->rx_dma_chan);
1007 ret = -EIO;
1008 tegra_qspi_dump_regs(tqspi);
1009 tegra_qspi_flush_fifos(tqspi);
1010 reset_control_assert(tqspi->rst);
1011 udelay(2);
1012 reset_control_deassert(tqspi->rst);
1013 goto exit;
1014 }
1015
1016 if (tqspi->tx_status || tqspi->rx_status) {
1017 ret = -EIO;
1018 dev_err(tqspi->dev, "error in transfer: %d\n", ret);
1019 tegra_qspi_dump_regs(tqspi);
1020 goto exit;
1021 }
1022
1023 msg->actual_length += xfer->len;
1024 xfer_phase++;
1025 }
1026
1027 ret = 0;
1028 exit:
1029 tegra_qspi_writel(tqspi, tqspi->def_command1_reg, QSPI_COMMAND1);
1030 msg->status = ret;
1031 spi_finalize_current_message(master);
1032 return ret;
1033 }
1034

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

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