Re: [PATCH] MIPS: KASLR: Fix sync_icache() trapped in loop when synci_step is zero

[Jinyang He]

Hi, Thomas,

On 12/02/2020 06:39 PM, Thomas Bogendoerfer wrote:
> On Wed, Dec 02, 2020 at 11:00:05AM +0800, Jinyang He wrote:
> > Reading synci_step by using rdhwr instruction may return zero if no cache
> > need be synchronized. On the one hand, to make sure all load operation and
> > store operation finished we do __sync() for every platform. On the other
> > hand, some platform need operate synci one time although step is zero.
> Should this be someting like: Avoid endless loop, if no synci is needed ?
>
> > diff --git a/arch/mips/kernel/relocate.c b/arch/mips/kernel/relocate.c
> > index 57bdd276..47aeb33 100644
> > --- a/arch/mips/kernel/relocate.c
> > +++ b/arch/mips/kernel/relocate.c
> > @@ -64,7 +64,7 @@ static void __init sync_icache(void *kbase, unsigned long kernel_length)
> >   			: "r" (kbase));
> >   
> >   		kbase += step;
> > -	} while (kbase < kend);
> > +	} while (step && kbase < kend);
> why not do a
>
> 	if (step == 0)
> 		return;
>
> before entering the loop ? According to MIPS32PRA no synci is needed,
> if stepi value is zero.

Thanks for your reply.

Most platforms do not need to do synci instruction operations
when synci_step is 0. But for example, the synci implementation
on Loongson64 platform has some changes. On the one hand, it
ensures that the memory access instructions have been completed.
On the other hand, it guarantees that all prefetch instructions
need to be fetched again. And its address information is useless.
Thus, only one synci operation is required when synci_step is 0
on Loongson64 platform. I guess that some other platforms have
similar implementations on synci, so add judgment conditions in
`while` to ensure that at least all platforms perform synci
operations once. For those platforms that do not need synci,
they just do one more operation similar to nop.

I will modify the submitted information and send v2.

> Thomas.
> PS: Does anybody know a reason, why this code doesn't use an old fashioned
> dache/icache flushing, which might be slower but would work also on
> legecy cores ?
For this, my thought is that different platforms using the cache
instruction to flush caches is inconsistent. Here is just a more
general way to flush these caches.

Thanks,
Jinyang.