Re: [PATCH v3 1/2] dt-bindings: riscv: Update l2 cache DT documentation to add support for SiFive FU740

From: Rob Herring
Date: Thu Dec 10 2020 - 22:48:24 EST


On Thu, 10 Dec 2020 15:58:02 +0530, Yash Shah wrote:
> The L2 cache controller in SiFive FU740 has 4 ECC interrupt sources as
> compared to 3 in FU540. Update the DT documentation accordingly with
> "compatible" and "interrupt" property changes.
>
> Signed-off-by: Yash Shah <yash.shah@xxxxxxxxxx>
> ---
> .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
> 1 file changed, 30 insertions(+), 4 deletions(-)
>

Reviewed-by: Rob Herring <robh@xxxxxxxxxx>