Re: [PATCH v3 0/9] Xilinx AI engine kernel driver

From: Jiaying Liang
Date: Mon Dec 14 2020 - 19:27:27 EST

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On 12/11/20 11:39 AM, Daniel Vetter wrote:

Hi all

On Fri, Dec 11, 2020 at 8:03 PM Alex Deucher<alexdeucher@xxxxxxxxx> wrote:

On Mon, Nov 30, 2020 at 3:25 AM Wendy Liang<wendy.liang@xxxxxxxxxx> wrote:

AI engine is the acceleration engine provided by Xilinx. These engines
provide high compute density for vector-based algorithms, and flexible
custom compute and data movement. It has core tiles for compute and
shim tiles to interface the FPGA fabric.

You can check the AI engine architecture document for more hardware details:
https://www.xilinx.com/support/documentation/architecture-manuals/am009-versal-ai-engine.pdf

This patch series adds a Linux kernel driver to manage the Xilinx AI
engine array device and AI engine partitions (groups of AI engine tiles
dedicated to an application).

Hi Wendy,

I think it would be good to provide an overview of how your stack
works in general. That would give reviewers a better handle on how
all of this fits together. I'd suggest including an overview in the
cover letter and also in the commit message and/or as a comment in the
code in one of the patches. I'm not really an expert when it comes to
FPGAs, but this basically looks like a pretty low level interface to
set up the data fabric for a kernel that will run on the soft logic or
maybe the microcontroller on the board. It doesn't have to be super
detailed, just a nice flow for how you might use this. E.g.,

Userspace uses ioctls X, Y, Z to configure the data fabric for the
FPGA kernel. The kernels can run on... . DMA access to system memory
for data sets can be allocated using ioctl A. DMA access is limited
by... . The user can then load the FPGA kernel on to one of the
engines using ioctl B and finally they can kick off the whole thing
using ioctl C. FPGA kernels are compiled using YYY toolchain and use
use the following runtime (link to runtime) to configure the data
fabric using ioctls X, Y, Z.

At least for drm drivers we ideally have that as a .rst file in
Documentation/. With that you can even do full svg graphs, or just dot
graphs, of the overall stack if you really want to go overboard :-)

It would also be good to go over the security implications of the
design. E.g., can the FPGA kernel(s) access the DMA engine directly,
or is it limited to just the DMA regions set up by the ioctls? Also,
does the hardware and software design allow for multiple users? If
so, how does that work?

I've also seen indications that there's some on-chip or on-card
memory. How that's planned to be used and whether we want to manage
this (maybe even with something like ttm) would be good to understand.

All excellent questions from Alex, just figured I add some more.

Cheers, Daniel

Hi Alex, Daniel,

Below is an overview of the driver.

AI engine kernel driver manages Xilinx AI engine device. An AI engine device
contains cores tiles and SHIM tiles. Core tiles are the computation tiles
, the SHIM tiles are the tiles interfacing to external components.

          +--------+--------+--------+--------+
         | Core        | Core        | Core | Core | ...
         |      |                | |          |
          +-----------------------------------+
         | Core        | Core | Core        | Core     | ...
           |          |        | |         |
          +--------+--------+--------+---------
           ...
          +--------+--------+-----------------+
          | SHIM | SHIM       | SHIM       |SHIM        |
          | PL      | PL       | PL            |PL | NOC |
          +---+----+---+----+---+-----+-------+
AXI Streams   |        |          |    |    |AXI MM
                     |        |        | |    |
Events Singals |        |        |    |    |
               |        |          | |    |
             |        |          | |    |
          +---+--------+--------+-----+ +--+------+
          |       FPGA                  | |   NOC        |
          | | |        |
          +---------------------------+ +--+-------+
                                           |
                                           |
                                       +---+------+
                                       |   DDR   |
                                       +----------+

Each Core tile contains computing module, local memory and DMA module. The
local memory DMA module takes data from or to the AXI streams and writes
it to or reads it from the local memory. The computing module can also
directly get/put data from/to the AXI stream. The AIE SHIM enables AIE tiles
to get/put data from/to AXI streams from FPGA, enables external master to
access AI engine address space through AXI MM. SHIM NoC module has DMA engine,
which can access extern memory though AXI MM and push it to internal AXI
streams.

At runtime, the AI engine tiles interconnection needs to be configured so that
it can get fetch data from external components or adjacent tiles, and AI engine
core program needs to be loaded. And then user application can push data to the
AI engine array and start/stop AI engine core. AI engine device errors can be
raised as events, the AI engine kernel driver listens to the events interrupt
to monitor runtime async device errors.

Instead of application directly interacting with the AI engine kernel APIs, user
application/libraries interacts with AI engine userspace library:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/aienginev2
It provides cross OSes low level functional abstraction such as how to connect one
stream port to another stream port, how to configure core tile local DMA.

The AI engine library can be used by other runtime libraries such as Xilinx runtime (XRT)
library: https://xilinx.github.io/XRT/master/html/index.html,
which provides acceleration abstraction for Xilinx accelerators, it has extensions
to interface to other acceleration framework such as OpenCL.
XRT provides buffer handling abstractions for user application to share data between
applicaiton and devices.

Here is an example of application runtime stack:

            +----------------------------+
            |      Application          |
            | |
            +----------------------------+
            |       XRT                                        |
            | |
            +----------------------------+
            |      AIE Library             |
            | |
         +----------------------------+
    +----------------------------------------+
Kern +----------------------------+
            |         AIE Partition                        +--+
           +----------------------------+    |
                |----------------------------+
            +----------------------------+
             |         AIE Device          |
             | |
            +----------------------------+

The AI engine kernel driver provides the following user interfaces:
* AIE device driver is the root device driver to manage the partitions of
   of the AI engine device array. AI engine array can be partitioned into
   column wised isolated partitions. Each applicaiton can only access its
   own partitions.
* AIE device driver monitors the interrupt from the AI enigne device. All
   AI engine tiles shared the same interrupt for error events.
* AIE partition driver controls address mapping and access of the
   registers/local memories of the tiles within a partition.
   * It provides mmap operation to enable application to direclty access the
     tiles local memories for small data update such as parameter update for
     performance.
   * It provides mmap operatio to map all the registers as readonly for
     application to poll registers efficiently to check status.
   * It provides ioctl for userspace to pass I/O commands to write/mask write
     the registers. How to configure is defined by userspace. Userspace will
     pass the I/O commands sequence to the kernel driver, and kernel driver
     will validate the commands before it writes to the registers.
   * It provides ioctl to import dmabuf and ioctl to configure the the DMA module
     in the SHIM tile which can access memory outside AI engine array.

The buffer management is out of this driver. In the above example, user application
uses Xilinx runtime(XRT), XRT is the one to manage the buffers.

Best Regards,

Wendy

Thanks,

Alex

v3:
* unlock AIE dev mutex after failed to gain the partition lock in
errors handing
* replace pointer with __u64 and enum with __u32 in ioctl

v2:
* Fix dtschema check errors
* Fix test bot warning on interrupt implementation. Removed set but
unused varaible.
* Fix compilation unused function warning of firmware change in case
ZynqMP firmware is not configured
* There are other warning on ZynqMP firmware reported from testbot
which is not introduced by this patch set.
"[PATCH] firmware: xlnx-zynqmp: fix compilation warning" is submitted
for those fixes.

Izhar Ameer Shaikh (1):
firmware: xilinx: Add IOCTL support for AIE ISR Clear

Nishad Saraf (2):
misc: xilinx-ai-engine: Add support to request device management
services
misc: xilinx-ai-engine: Add support for servicing error interrupts

Wendy Liang (6):
dt-binding: soc: xilinx: ai-engine: Add AI engine binding
misc: Add Xilinx AI engine device driver
misc: xilinx-ai-engine: Implement AI engine cleanup sequence
misc: xilinx-ai-engine: expose AI engine tile memories to userspace
misc: xilinx-ai-engine: add setting shim dma bd operation
misc: xilinx-ai-engine: add request and release tiles

.../bindings/soc/xilinx/xlnx,ai-engine.yaml | 126 ++++
MAINTAINERS | 8 +
drivers/firmware/xilinx/zynqmp.c | 14 +
drivers/misc/Kconfig | 12 +
drivers/misc/Makefile | 1 +
drivers/misc/xilinx-ai-engine/Makefile | 16 +
drivers/misc/xilinx-ai-engine/ai-engine-aie.c | 608 +++++++++++++++++++
drivers/misc/xilinx-ai-engine/ai-engine-clock.c | 245 ++++++++
drivers/misc/xilinx-ai-engine/ai-engine-dev.c | 496 ++++++++++++++++
drivers/misc/xilinx-ai-engine/ai-engine-dma.c | 481 +++++++++++++++
drivers/misc/xilinx-ai-engine/ai-engine-internal.h | 519 ++++++++++++++++
.../misc/xilinx-ai-engine/ai-engine-interrupt.c | 659 +++++++++++++++++++++
drivers/misc/xilinx-ai-engine/ai-engine-mem.c | 275 +++++++++
drivers/misc/xilinx-ai-engine/ai-engine-part.c | 635 ++++++++++++++++++++
drivers/misc/xilinx-ai-engine/ai-engine-res.c | 219 +++++++
drivers/misc/xilinx-ai-engine/ai-engine-reset.c | 159 +++++
include/linux/firmware/xlnx-zynqmp.h | 8 +
include/uapi/linux/xlnx-ai-engine.h | 238 ++++++++
18 files changed, 4719 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soc/xilinx/xlnx,ai-engine.yaml
create mode 100644 drivers/misc/xilinx-ai-engine/Makefile
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-aie.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-clock.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dev.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-dma.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-internal.h
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-interrupt.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-mem.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-part.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-res.c
create mode 100644 drivers/misc/xilinx-ai-engine/ai-engine-reset.c
create mode 100644 include/uapi/linux/xlnx-ai-engine.h

--
2.7.4

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Next message: Pavel Begunkov: "[PATCH v1 2/6] iov_iter: optimise bvec iov_iter_advance()"
Previous message: Stephen Rothwell: "linux-next: manual merge of the nfs tree with Linus' tree"
In reply to: Daniel Vetter: "Re: [PATCH v3 0/9] Xilinx AI engine kernel driver"
Next in thread: Daniel Vetter: "Re: [PATCH v3 0/9] Xilinx AI engine kernel driver"
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