Re: [PATCH] clk: exynos7: Mark aclk_fsys1_200 as critical

[Stephen Boyd]

Not sure why this wasn't picked up in the samsung PR. Can you resend?

> diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
> index c1ff715e960c..1048d83f097b 100644
> --- a/drivers/clk/samsung/clk-exynos7.c
> +++ b/drivers/clk/samsung/clk-exynos7.c
> @@ -538,7 +538,8 @@ static const struct samsung_gate_clock top1_gate_clks[] __initconst = {
>                 ENABLE_ACLK_TOP13, 28, CLK_SET_RATE_PARENT |
>                 CLK_IS_CRITICAL, 0),
>         GATE(CLK_ACLK_FSYS1_200, "aclk_fsys1_200", "dout_aclk_fsys1_200",
> -               ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT, 0),
> +               ENABLE_ACLK_TOP13, 24, CLK_SET_RATE_PARENT |
> +               CLK_IS_CRITICAL, 0),
>  

Please put a comment in the code why a clk is critical.