Re: [PATCH 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding

From: Liu Ying
Date: Tue Dec 22 2020 - 03:29:53 EST

Hi Laurent,

On Tue, 2020-12-22 at 09:49 +0200, Laurent Pinchart wrote:
> Hi Liu,
>
> On Tue, Dec 22, 2020 at 09:36:37AM +0200, Laurent Pinchart wrote:
> > On Thu, Dec 17, 2020 at 05:59:30PM +0800, Liu Ying wrote:
> > > This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB).
> > >
> > > Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
> > > ---
> > > .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 185 +++++++++++++++++++++
> > > 1 file changed, 185 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > > new file mode 100644
> > > index 00000000..4e5ff6f
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml
> > > @@ -0,0 +1,185 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fschemas%2Fdisplay%2Fbridge%2Ffsl%2Cimx8qxp-ldb.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7C3c38a4426c5e40581a1c08d8a64e2e13%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637442201999086534%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=fr9ARb0ct7BDgvzllfXENvJ5KKTLD63PNOaDSkVzqFQ%3D&amp;reserved=0
> > > +$schema: https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevicetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cvictor.liu%40nxp.com%7C3c38a4426c5e40581a1c08d8a64e2e13%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637442201999086534%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=LVh6NVTyid8M0%2FDPbBfJQ5%2BhuBxMKw4%2BK9u%2FSIkeaVw%3D&amp;reserved=0
> > > +
> > > +title: Freescale i.MX8qm/qxp LVDS Display Bridge
> > > +
> > > +maintainers:
> > > + - Liu Ying <victor.liu@xxxxxxx>
> > > +
> > > +description: |
> > > + The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels.
> > > +
> > > + For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color
> > > + format and can map the input to VESA or JEIDA standards. The two channels
> > > + cannot be used simultaneously, that is to say, the user should pick one of
> > > + them to use. Two LDB channels from two LDB instances can work together in
> > > + LDB split mode to support a dual link LVDS display. The channel indexes
> > > + have to be different. Channel0 outputs odd pixels and channel1 outputs
> > > + even pixels.
> >
> > In this case, does the display controller output odd pixels and even
> > pixels separately to the two LVDS channels, with each channel
> > effectively be a separate LVDS encoder ? Could you give an example of DT
> > integration for dual-link LVDS support, with the display controller, two
> > LDB instances, and a dual-link LVDS panel ?
>
> I also can't find any mention of the LDB in IMX8MDQLQRM or IMX8DQXPRM.
> Am I missing something ?

i.MX8mq doesn't has LDB.

The i.MX8qxp RM calls LDB as pixel mapper.

This binding calls it 'LDB' for below reasons:
1) 'LDB' is a shorter name.

2) Our internal i.MX8qm/qxp documentations do mention that pixel mapper
uses LDB logic and is based on i.MX6 LDB.

3) Patch 10/14 creates a 'imx-ldb-helper' which can be potentially used
by i.MX6qdl/sx LDBs. So, it will be a consistent name.

Do you think if it will be ok if I mention 'pixel mapper' as a side
note in the next version?

Liu Ying

>
> > > +
> > > + For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel
> > > + input color format. The two channels can be used simultaneously, either
> > > + in dual mode or split mode. In dual mode, the two channels output identical
> > > + data. In split mode, channel0 outputs odd pixels and channel1 outputs even
> > > + pixels.
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - fsl,imx8qm-ldb
> > > + - fsl,imx8qxp-ldb
> > > +
> > > + "#address-cells":
> > > + const: 1
> > > +
> > > + "#size-cells":
> > > + const: 0
> > > +
> > > + clocks:
> > > + items:
> > > + - description: pixel clock
> > > + - description: bypass clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: pixel
> > > + - const: bypass
> > > +
> > > + power-domains:
> > > + maxItems: 1
> > > +
> > > + fsl,syscon:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description: |
> > > + A phandle which points to Control and Status Registers(CSR) module.
> > > +
> > > + fsl,companion-ldb:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description: |
> > > + A phandle which points to companion LDB which is used in LDB split mode.
> > > +
> > > +patternProperties:
> > > + "^channel@[0-1]$":
> > > + type: object
> > > + description: Represents a channel of LDB.
> > > +
> > > + properties:
> > > + "#address-cells":
> > > + const: 1
> > > +
> > > + "#size-cells":
> > > + const: 0
> > > +
> > > + reg:
> > > + description: The channel index.
> > > + enum: [ 0, 1 ]
> > > +
> > > + phys:
> > > + description: A phandle to the phy module representing the LVDS PHY.
> > > + maxItems: 1
> > > +
> > > + phy-names:
> > > + const: lvds_phy
> > > +
> > > + port@0:
> > > + type: object
> > > + description: Input port of the channel.
> > > +
> > > + properties:
> > > + reg:
> > > + const: 0
> > > +
> > > + required:
> > > + - reg
> > > +
> > > + port@1:
> > > + type: object
> > > + description: Output port of the channel.
> > > +
> > > + properties:
> > > + reg:
> > > + const: 1
> > > +
> > > + required:
> > > + - reg
> > > +
> > > + required:
> > > + - "#address-cells"
> > > + - "#size-cells"
> > > + - reg
> > > + - phys
> > > + - phy-names
> > > +
> > > + additionalProperties: false
> > > +
> > > +required:
> > > + - compatible
> > > + - "#address-cells"
> > > + - "#size-cells"
> > > + - clocks
> > > + - clock-names
> > > + - power-domains
> > > + - fsl,syscon
> > > + - channel@0
> > > + - channel@1
> > > +
> > > +allOf:
> > > + - if:
> > > + properties:
> > > + compatible:
> > > + contains:
> > > + const: fsl,imx8qm-ldb
> > > + then:
> > > + properties:
> > > + fsl,companion-ldb: false
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/firmware/imx/rsrc.h>
> > > + ldb {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + compatible = "fsl,imx8qxp-ldb";
> > > + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
> > > + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
> > > + clock-names = "pixel", "bypass";
> > > + power-domains = <&pd IMX_SC_R_LVDS_0>;
> > > + fsl,syscon = <&mipi_lvds_0_csr>;
> > > +
> > > + channel@0 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <0>;
> > > + phys = <&mipi_lvds_0_phy>;
> > > + phy-names = "lvds_phy";
> > > +
> > > + port@0 {
> > > + reg = <0>;
> > > +
> > > + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint {
> > > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>;
> > > + };
> > > + };
> > > + };
> > > +
> > > + channel@1 {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > + reg = <1>;
> > > + phys = <&mipi_lvds_0_phy>;
> > > + phy-names = "lvds_phy";
> > > +
> > > + port@0 {
> > > + reg = <0>;
> > > +
> > > + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint {
> > > + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>;
> > > + };
> > > + };
> > > + };
> > > + };
> >
> > --
> > Regards,
> >
> > Laurent Pinchart