Re: [PATCH 06/11] dts: bindings: Document device tree bindings for ETE

From: Suzuki K Poulose
Date: Mon Jan 04 2021 - 09:43:06 EST


Hi Rob,

On 1/3/21 5:02 PM, Rob Herring wrote:
On Wed, Dec 23, 2020 at 03:33:38PM +0530, Anshuman Khandual wrote:
From: Suzuki K Poulose <suzuki.poulose@xxxxxxx>

Document the device tree bindings for Embedded Trace Extensions.
ETE can be connected to legacy coresight components and thus
could optionally contain a connection graph as described by
the CoreSight bindings.

Cc: devicetree@xxxxxxxxxxxxxxx
Cc: Mathieu Poirier <mathieu.poirier@xxxxxxxxxx>
Cc: Mike Leach <mike.leach@xxxxxxxxxx>
Cc: Rob Herring <robh@xxxxxxxxxx>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@xxxxxxx>
Signed-off-by: Anshuman Khandual <anshuman.khandual@xxxxxxx>
---
Documentation/devicetree/bindings/arm/ete.txt | 41 +++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/ete.txt

Bindings are in schema format now, please convert this.


Sure, will do that.


diff --git a/Documentation/devicetree/bindings/arm/ete.txt b/Documentation/devicetree/bindings/arm/ete.txt
new file mode 100644
index 0000000..b52b507
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/ete.txt
@@ -0,0 +1,41 @@
+Arm Embedded Trace Extensions
+
+Arm Embedded Trace Extensions (ETE) is a per CPU trace component that
+allows tracing the CPU execution. It overlaps with the CoreSight ETMv4
+architecture and has extended support for future architecture changes.
+The trace generated by the ETE could be stored via legacy CoreSight
+components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer
+Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
+legacy CoreSight components, a node must be listed per instance, along
+with any optional connection graph as per the coresight bindings.
+See bindings/arm/coresight.txt.
+
+** ETE Required properties:
+
+- compatible : should be one of:
+ "arm,embedded-trace-extensions"
+
+- cpu : the CPU phandle this ETE belongs to.

If this is 1:1 with CPUs, then perhaps it should be a child node of the
CPU nodes.

Yes, it is 1:1 with the CPUs. I have tried to keep this aligned with that of
"coresight-etm4x". The same driver handles both. The only reason why this
was separated from the "coresight.txt" is to describe the new configurations
possible (read, TRBE).

That said, I am happy to move this under the CPU, if Mathieu is happy with
the diversion.

Thanks for the review.

Suzuki