Re: [PATCH 4/5] clk: qcom: Add A7 PLL support

From: Konrad Dybcio
Date: Mon Jan 04 2021 - 10:31:15 EST

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Hi,

could you explicitly state in the probe function (or just in the driver in general, as there's not much more?) and the config structs that the target SoC is X55?

A few more SoCs (MDM9607, MSM8x26 and some others) also use what's known as "A7PLL" downstream, but all of them have a separate configuration for their specific PLLs, which aren't compatible with each other.

Konrad

Next message: Kishon Vijay Abraham I: "[PATCH v9 11/17] PCI: cadence: Implement ->msi_map_irq() ops"
Previous message: Kishon Vijay Abraham I: "[PATCH v9 09/17] PCI: endpoint: Add pci_epf_ops for epf drivers to expose function specific attrs"
In reply to: Manivannan Sadhasivam: "[PATCH 4/5] clk: qcom: Add A7 PLL support"
Next in thread: Manivannan Sadhasivam: "[PATCH 5/5] clk: qcom: Add SDX55 APCS clock controller support"
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