[PATCH 1/2] rtc: pcf2127: Disable Power-On Reset Override

[Philipp Rosenberger]

If the PCF2127/2129 has lost all power and is then powered again it goes
into "Power-On Reset Override" mode. In this mode the RTC seems to work
fine. Also the watchdog can be configured. The watchdog timer counts as
expected and the WDTF (watchdog timer flag) gets set. But no interrupt
is generated on the INT pin. The same applies to the alarm function.

The POR_OVRD bit on the Control_1 register must be cleared first. In
some cases the bootloader or firmware might have done this already. But
we clear the bit nevertheless to guarantee correct behavior the
watchdog and alarm function.

Signed-off-by: Philipp Rosenberger <p.rosenberger@xxxxxxxxxx>
---
 drivers/rtc/rtc-pcf2127.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c
index 39a7b5116aa4..39c28bac4d1a 100644
--- a/drivers/rtc/rtc-pcf2127.c
+++ b/drivers/rtc/rtc-pcf2127.c
@@ -612,6 +612,19 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap,
 		ret = devm_rtc_nvmem_register(pcf2127->rtc, &nvmem_cfg);
 	}
 
+	/*
+	 * Disable the Power-On Reset Override facility to start normal
+	 * operation. If the operation should fail, just move on. The RTC should
+	 * work fine, but functions like watchdog and alarm interrupts might
+	 * not work.
+	 */
+	ret = regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1,
+				PCF2127_BIT_CTRL1_POR_OVRD);
+	if (ret) {
+		dev_err(dev, "%s: can't disable PORO (ctrl1).\n", __func__);
+		dev_warn(dev, "Watchdog and alarm functions might not work properly\n");
+	}
+
 	/*
 	 * Watchdog timer enabled and reset pin /RST activated when timed out.
 	 * Select 1Hz clock source for watchdog timer.
-- 
2.29.2