Re: [PATCH] iommu/io-pgtable-arm: Allow non-coherent masters to use system cache

[Sai Prakash Ranjan]

Hi Will,

On 2021-01-06 17:26, Will Deacon wrote:
> On Thu, Dec 24, 2020 at 12:10:07PM +0530, Sai Prakash Ranjan wrote:
> > commit ecd7274fb4cd ("iommu: Remove unused IOMMU_SYS_CACHE_ONLY flag")
> > removed unused IOMMU_SYS_CACHE_ONLY prot flag and along with it went
> > the memory type setting required for the non-coherent masters to use
> > system cache. Now that system cache support for GPU is added, we will
> > need to mark the memory as normal sys-cached for GPU to use system 
> > cache.
> > Without this, the system cache lines are not allocated for GPU. We use
> > the IO_PGTABLE_QUIRK_ARM_OUTER_WBWA quirk instead of a page protection
> > flag as the flag cannot be exposed via DMA api because of no in-tree
> > users.
> >
> > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@xxxxxxxxxxxxxx>
> > ---
> >  drivers/iommu/io-pgtable-arm.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/drivers/iommu/io-pgtable-arm.c 
> > b/drivers/iommu/io-pgtable-arm.c
> > index 7c9ea9d7874a..3fb7de8304a2 100644
> > --- a/drivers/iommu/io-pgtable-arm.c
> > +++ b/drivers/iommu/io-pgtable-arm.c
> > @@ -415,6 +415,9 @@ static arm_lpae_iopte arm_lpae_prot_to_pte(struct 
> > arm_lpae_io_pgtable *data,
> >  		else if (prot & IOMMU_CACHE)
> >  			pte |= (ARM_LPAE_MAIR_ATTR_IDX_CACHE
> >  				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
> > +		else if (data->iop.cfg.quirks & IO_PGTABLE_QUIRK_ARM_OUTER_WBWA)
> > +			pte |= (ARM_LPAE_MAIR_ATTR_IDX_INC_OCACHE
> > +				<< ARM_LPAE_PTE_ATTRINDX_SHIFT);
> >  	}
>
> drivers/iommu/io-pgtable.c currently documents this quirk as applying 
> only
> to the page-table walker. Given that we only have one user at the 
> moment,
> I think it's ok to change that, but please update the comment.

Sure, how about this change in comment:

         * IO_PGTABLE_QUIRK_ARM_OUTER_WBWA: Override the 
outer-cacheability
-        *      attributes set in the TCR for a non-coherent page-table 
walker.
+        *      attributes set in the TCR for a non-coherent page-table 
walker
+        *      and also to set the correct cacheability attributes to 
use an
+        *      outer level of cache for non-coherent masters.

> We also need to decide on whether we want to allow the quirk to be 
> passed
> if the coherency of the page-table walker differs from the DMA device, 
> since
> we have these combinations:
>
> 	Coherent walker?	IOMMU_CACHE	IO_PGTABLE_QUIRK_ARM_OUTER_WBWA
> 0:	N			0		0
> 1:	N			0		1
> 2:	N			1		0
> 3:	N			1		1
> 4:	Y			0		0
> 5:	Y			0		1
> 6:	Y			1		0
> 7:	Y			1		1
>
> Some of them are obviously bogus, such as (7), but I don't know what to
> do about cases such as (3) and (5).

I thought this was already decided when IOMMU_SYS_CACHE_ONLY prot flag 
was
added in this same location [1]. dma-coherent masters can use the normal
cached memory type to use the system cache and non dma-coherent masters
willing to use system cache should use normal sys-cached memory type 
with
this quirk.

[1] 
https://lore.kernel.org/linux-arm-msm/20190516093020.18028-1-vivek.gautam@xxxxxxxxxxxxxx/

Thanks,
Sai

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