RE: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support

[Shameerali Kolothum Thodi]

> -----Original Message-----
> From: wanghuiqiang
> Sent: 06 January 2021 09:22
> To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@xxxxxxxxxx>;
> 'Ard Biesheuvel' <ardb@xxxxxxxxxx>
> Cc: 'Marc Zyngier' <maz@xxxxxxxxxx>; 'eric.auger@xxxxxxxxxx'
> <eric.auger@xxxxxxxxxx>; 'linux-kernel@xxxxxxxxxxxxxxx'
> <linux-kernel@xxxxxxxxxxxxxxx>; 'linux-arm-kernel@xxxxxxxxxxxxxxxxxxx'
> <linux-arm-kernel@xxxxxxxxxxxxxxxxxxx>; Linuxarm <linuxarm@xxxxxxxxxx>;
> xuwei (O) <xuwei5@xxxxxxxxxx>
> Subject: 答复: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
> 
> Hi Ard and all,
> 
> The issue is root caused, it is introduced by BIOS new feature implemented.
> With old BIOS，we use static MADT table and the GICV/GICH is set to 0 and
> reported this table to OS. But we added new features which will dynamic
> update MADT table based on some external input, the developer is set
> GICV/GICH as what we have done like previous generation chipset code did.
> But in fact, there is different compared with old generation chipset code.
> I'll let my internal team know this and fix this issue in later BIOS release.

Thanks Wanghuiqiang for your efforts and confirming the issue.

Hi Marc,

Considering the fact that we have systems out there with the faulty BIOS, and it is
not necessarily everyone will be keen to update the BIOS, I think it is better to
address this in kernel as well.

As discussed earlier, please consider the SRE bit based solution to make the logic
more robust irrespective of what BIOS provides.

(I don’t have an erratum id for this as I am told we keep that for Hardware issues
only, but we are using DTS202101070OAGUIP1L00 to track the issue and can be
used as reference).

Thanks,
Shameer 

> Thanks!
> 
> -----邮件原件-----
> 发件人: wanghuiqiang
> 发送时间: 2020年12月15日 15:49
> 收件人: Shameerali Kolothum Thodi
> <shameerali.kolothum.thodi@xxxxxxxxxx>; Ard Biesheuvel
> <ardb@xxxxxxxxxx>
> 抄送: Marc Zyngier <maz@xxxxxxxxxx>; eric.auger@xxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Linuxarm
> <linuxarm@xxxxxxxxxx>; xuwei (O) <xuwei5@xxxxxxxxxx>
> 主题: 答复: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
> 
> Sorry response late.
> Hi Shameer & Ard,
> 
> Could you let me know which firmware you are using? If the difference is Madt
> table vGIC your pointed , they are the same. We changed the vGIC memory
> base address at very early design stage.
> 
> Thanks！
> 
> -----邮件原件-----
> 发件人: Shameerali Kolothum Thodi
> 发送时间: 2020年12月2日 16:23
> 收件人: Ard Biesheuvel <ardb@xxxxxxxxxx>
> 抄送: Marc Zyngier <maz@xxxxxxxxxx>; eric.auger@xxxxxxxxxx;
> linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; Linuxarm
> <linuxarm@xxxxxxxxxx>; wanghuiqiang <wanghuiqiang@xxxxxxxxxx>; xuwei
> (O) <xuwei5@xxxxxxxxxx>
> 主题: RE: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy support
> 
> [+]
> 
> > -----Original Message-----
> > From: Ard Biesheuvel [mailto:ardb@xxxxxxxxxx]
> > Sent: 30 November 2020 18:32
> > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@xxxxxxxxxx>
> > Cc: Marc Zyngier <maz@xxxxxxxxxx>; eric.auger@xxxxxxxxxx;
> > linux-kernel@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx;
> > Linuxarm <linuxarm@xxxxxxxxxx>
> > Subject: Re: [PATCH] irqchip/gic-v3: Check SRE bit for GICv2 legacy
> > support
> >
> ...
> 
> >
> > Any clue why production D06 firmware deviates from the D06 port that
> > exists in Tianocore's edk2-platforms repository? Because that version
> > does not have this bug, and I wonder why that code was upstreamed at
> > all if a substantially different version gets shipped with production
> > hardware.
> 
> Ok. Thanks for pointing this out. I have informed our UEFI team about this.
> They will check Internally and clarify.
> 
> Regards,
> Shameer