Re: [PATCH v7 4/5] PCI: tegra: Remove platform driver support for ZRX-DC compliant PHY

From: kernel test robot
Date: Thu Jan 07 2021 - 13:48:35 EST

Hi Shradha,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on pci/next]
[also build test WARNING on linus/master v5.11-rc2 next-20210104]
[cannot apply to robh/for-next linux/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url: https://github.com/0day-ci/linux/commits/Shradha-Todi/Add-support-to-handle-ZRX-DC-Compliant-PHYs/20210108-001626
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-a005-20210107 (attached as .config)
compiler: clang version 12.0.0 (https://github.com/llvm/llvm-project 5c951623bc8965fa1e89660f2f5f4a2944e4981a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# https://github.com/0day-ci/linux/commit/a626b81436de9ab5c0c0bc9785fbc64549ea0f3a
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Shradha-Todi/Add-support-to-handle-ZRX-DC-Compliant-PHYs/20210108-001626
git checkout a626b81436de9ab5c0c0bc9785fbc64549ea0f3a
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-tegra194.c:2063:4: warning: variable 'phy_zrxdc_count' is uninitialized when used here [-Wuninitialized]
phy_zrxdc_count++;
^~~~~~~~~~~~~~~
drivers/pci/controller/dwc/pcie-tegra194.c:1953:30: note: initialize the variable 'phy_zrxdc_count' to silence this warning
unsigned int phy_zrxdc_count;
^
= 0
1 warning generated.


vim +/phy_zrxdc_count +2063 drivers/pci/controller/dwc/pcie-tegra194.c

1948
1949 static int tegra_pcie_dw_probe(struct platform_device *pdev)
1950 {
1951 const struct tegra_pcie_dw_of_data *data;
1952 struct device *dev = &pdev->dev;
1953 unsigned int phy_zrxdc_count;
1954 struct resource *atu_dma_res;
1955 struct tegra_pcie_dw *pcie;
1956 struct pcie_port *pp;
1957 struct dw_pcie *pci;
1958 struct phy **phys;
1959 char *name;
1960 int ret;
1961 u32 i;
1962
1963 data = of_device_get_match_data(dev);
1964
1965 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1966 if (!pcie)
1967 return -ENOMEM;
1968
1969 pci = &pcie->pci;
1970 pci->dev = &pdev->dev;
1971 pci->ops = &tegra_dw_pcie_ops;
1972 pci->n_fts[0] = N_FTS_VAL;
1973 pci->n_fts[1] = FTS_VAL;
1974 pci->version = 0x490A;
1975
1976 pp = &pci->pp;
1977 pp->num_vectors = MAX_MSI_IRQS;
1978 pcie->dev = &pdev->dev;
1979 pcie->mode = (enum dw_pcie_device_mode)data->mode;
1980
1981 ret = tegra_pcie_dw_parse_dt(pcie);
1982 if (ret < 0) {
1983 const char *level = KERN_ERR;
1984
1985 if (ret == -EPROBE_DEFER)
1986 level = KERN_DEBUG;
1987
1988 dev_printk(level, dev,
1989 dev_fmt("Failed to parse device tree: %d\n"),
1990 ret);
1991 return ret;
1992 }
1993
1994 ret = tegra_pcie_get_slot_regulators(pcie);
1995 if (ret < 0) {
1996 const char *level = KERN_ERR;
1997
1998 if (ret == -EPROBE_DEFER)
1999 level = KERN_DEBUG;
2000
2001 dev_printk(level, dev,
2002 dev_fmt("Failed to get slot regulators: %d\n"),
2003 ret);
2004 return ret;
2005 }
2006
2007 if (pcie->pex_refclk_sel_gpiod)
2008 gpiod_set_value(pcie->pex_refclk_sel_gpiod, 1);
2009
2010 pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
2011 if (IS_ERR(pcie->pex_ctl_supply)) {
2012 ret = PTR_ERR(pcie->pex_ctl_supply);
2013 if (ret != -EPROBE_DEFER)
2014 dev_err(dev, "Failed to get regulator: %ld\n",
2015 PTR_ERR(pcie->pex_ctl_supply));
2016 return ret;
2017 }
2018
2019 pcie->core_clk = devm_clk_get(dev, "core");
2020 if (IS_ERR(pcie->core_clk)) {
2021 dev_err(dev, "Failed to get core clock: %ld\n",
2022 PTR_ERR(pcie->core_clk));
2023 return PTR_ERR(pcie->core_clk);
2024 }
2025
2026 pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2027 "appl");
2028 if (!pcie->appl_res) {
2029 dev_err(dev, "Failed to find \"appl\" region\n");
2030 return -ENODEV;
2031 }
2032
2033 pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
2034 if (IS_ERR(pcie->appl_base))
2035 return PTR_ERR(pcie->appl_base);
2036
2037 pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
2038 if (IS_ERR(pcie->core_apb_rst)) {
2039 dev_err(dev, "Failed to get APB reset: %ld\n",
2040 PTR_ERR(pcie->core_apb_rst));
2041 return PTR_ERR(pcie->core_apb_rst);
2042 }
2043
2044 phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
2045 if (!phys)
2046 return -ENOMEM;
2047
2048 for (i = 0; i < pcie->phy_count; i++) {
2049 name = kasprintf(GFP_KERNEL, "p2u-%u", i);
2050 if (!name) {
2051 dev_err(dev, "Failed to create P2U string\n");
2052 return -ENOMEM;
2053 }
2054 phys[i] = devm_phy_get(dev, name);
2055 kfree(name);
2056 if (IS_ERR(phys[i])) {
2057 ret = PTR_ERR(phys[i]);
2058 if (ret != -EPROBE_DEFER)
2059 dev_err(dev, "Failed to get PHY: %d\n", ret);
2060 return ret;
2061 }
2062 if (phy_property_present(phys[i], "phy-zrxdc-compliant"))
> 2063 phy_zrxdc_count++;
2064 }
2065
2066 if ((pcie->phy_count) && (pcie->phy_count == phy_zrxdc_count))
2067 pci->phy_zrxdc_compliant = true;
2068 else
2069 pci->phy_zrxdc_compliant = false;
2070
2071 pcie->phys = phys;
2072
2073 atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2074 "atu_dma");
2075 if (!atu_dma_res) {
2076 dev_err(dev, "Failed to find \"atu_dma\" region\n");
2077 return -ENODEV;
2078 }
2079 pcie->atu_dma_res = atu_dma_res;
2080
2081 pci->atu_size = resource_size(atu_dma_res);
2082 pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
2083 if (IS_ERR(pci->atu_base))
2084 return PTR_ERR(pci->atu_base);
2085
2086 pcie->core_rst = devm_reset_control_get(dev, "core");
2087 if (IS_ERR(pcie->core_rst)) {
2088 dev_err(dev, "Failed to get core reset: %ld\n",
2089 PTR_ERR(pcie->core_rst));
2090 return PTR_ERR(pcie->core_rst);
2091 }
2092
2093 pp->irq = platform_get_irq_byname(pdev, "intr");
2094 if (pp->irq < 0)
2095 return pp->irq;
2096
2097 pcie->bpmp = tegra_bpmp_get(dev);
2098 if (IS_ERR(pcie->bpmp))
2099 return PTR_ERR(pcie->bpmp);
2100
2101 platform_set_drvdata(pdev, pcie);
2102
2103 switch (pcie->mode) {
2104 case DW_PCIE_RC_TYPE:
2105 ret = devm_request_irq(dev, pp->irq, tegra_pcie_rp_irq_handler,
2106 IRQF_SHARED, "tegra-pcie-intr", pcie);
2107 if (ret) {
2108 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2109 ret);
2110 goto fail;
2111 }
2112
2113 ret = tegra_pcie_config_rp(pcie);
2114 if (ret && ret != -ENOMEDIUM)
2115 goto fail;
2116 else
2117 return 0;
2118 break;
2119
2120 case DW_PCIE_EP_TYPE:
2121 ret = devm_request_threaded_irq(dev, pp->irq,
2122 tegra_pcie_ep_hard_irq,
2123 tegra_pcie_ep_irq_thread,
2124 IRQF_SHARED | IRQF_ONESHOT,
2125 "tegra-pcie-ep-intr", pcie);
2126 if (ret) {
2127 dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq,
2128 ret);
2129 goto fail;
2130 }
2131
2132 ret = tegra_pcie_config_ep(pcie, pdev);
2133 if (ret < 0)
2134 goto fail;
2135 break;
2136
2137 default:
2138 dev_err(dev, "Invalid PCIe device type %d\n", pcie->mode);
2139 }
2140
2141 fail:
2142 tegra_bpmp_put(pcie->bpmp);
2143 return ret;
2144 }
2145

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@xxxxxxxxxxxx

Attachment: .config.gz
Description: application/gzip