[PATCH 5.10 142/152] drm/i915/gt: Restore clear-residual mitigations for Ivybridge, Baytrail

From: Greg Kroah-Hartman
Date: Mon Jan 18 2021 - 07:02:41 EST

From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>

commit 09aa9e45863e9e25dfbf350bae89fc3c2964482c upstream.

The mitigation is required for all gen7 platforms, now that it does not
cause GPU hangs, restore it for Ivybridge and Baytrail.

Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@xxxxxxxxx>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx>
Cc: Bloomfield Jon <jon.bloomfield@xxxxxxxxx>
Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
Link: https://patchwork.freedesktop.org/patch/msgid/20210111225220.3483-2-chris@xxxxxxxxxxxxxxxxxx
(cherry picked from commit 008ead6ef8f588a8c832adfe9db201d9be5fd410)
Signed-off-by: Jani Nikula <jani.nikula@xxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>

drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1291,7 +1291,7 @@ int intel_ring_submission_setup(struct i

GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);

- if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) {
+ if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
err = gen7_ctx_switch_bb_init(engine);
if (err)
goto err_ring_unpin;