Re: [RFC PATCH 3/7] arm64: mm: use nGnRnE instead of nGnRE on Apple processors

From: Marc Zyngier
Date: Thu Jan 21 2021 - 11:27:54 EST

On 2021-01-21 15:12, Mohamed Mediouni wrote:
Please ignore that patch.

It turns out that the PCIe controller on Apple M1 expects posted
writes and so the memory range for it ought to be set nGnRE.
So, we need to use nGnRnE for on-chip MMIO and nGnRE for PCIe BARs.

The MAIR approach isn’t adequate for such a thing, so we’ll have to
look elsewhere.

Well, there isn't many alternative to having a memory type defined
in MAIR if you want to access your PCIe devices with specific

It probably means defining a memory type for PCI only, but:
- we only have a single free MT entry, and I'm not sure we can
afford to waste this on a specific platform (can we re-purpose
GRE instead?),
- we'd need to teach the PCI code to use this...


Jazz is not dead. It just smells funny...