Re: [PATCH v4 1/4] x86/cpufeatures: Enumerate #DB for bus lock detection

[Thomas Gleixner]

On Tue, Nov 24 2020 at 20:52, Fenghua Yu wrote:

> A bus lock is acquired though either split locked access to
> writeback (WB) memory or any locked access to non-WB memory. This is
> typically >1000 cycles slower than an atomic operation within a cache
> line. It also disrupts performance on other cores.
>
> Some CPUs have ability to notify the kernel by an #DB trap after a user
> instruction acquires a bus lock and is executed. This allows the kernel
> to enforce user application throttling or mitigations.

That's nice, but how does that interact with a data breakpoint on the
same location?

Also the information you pointed to in the cover letter

>  [1] Intel Instruction Set Extension Chapter 8:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

does not contain anything which is even remotely related to this patch
series. That chapter describes another bit in TEST_CTRL_MSR ...

Thanks,

        tglx