Re: [PATCH] MIPS: ralink: manage low reset lines

[John Crispin]

On 03.02.21 10:21, Sander Vanheule wrote:
> Reset lines with indices smaller than 8 are currently considered invalid
> by the rt2880-reset reset controller.
>
> The MT7621 SoC uses a number of these low reset lines. The DTS defines
> reset lines "hsdma", "fe", and "mcm" with respective values 5, 6, and 2.
> As a result of the above restriction, these resets cannot be asserted or
> de-asserted by the reset controller. In cases where the bootloader does
> not de-assert these lines, this results in e.g. the MT7621's internal
> switch staying in reset.
>
> Change the reset controller to only ignore the system reset, so all
> reset lines with index greater than 0 are considered valid.
>
> Signed-off-by: Sander Vanheule <sander@xxxxxxxxxxxxx>
Acked-by: John Crispin <john@xxxxxxxxxxx>
> ---
> This patch was tested on a TP-Link EAP235-Wall, with an MT7621DA SoC.
> The bootloader on this device would leave reset line 2 ("mcm") asserted,
> which caused the internal switch to be unresponsive on an uninterrupted
> boot from flash.
>
> When tftpboot was used in the bootloader to load an initramfs, it did
> initialise the internal switch, and cleared the mcm reset line. In this
> case the switch could be used from the OS. With this patch applied, the
> switch works both in an initramfs, and when (cold) booting from flash.
>
>   arch/mips/ralink/reset.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
> index 8126f1260407..274d33078c5e 100644
> --- a/arch/mips/ralink/reset.c
> +++ b/arch/mips/ralink/reset.c
> @@ -27,7 +27,7 @@ static int ralink_assert_device(struct reset_controller_dev *rcdev,
>   {
>   	u32 val;
>   
> -	if (id < 8)
> +	if (id == 0)
>   		return -1;
>   
>   	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
> @@ -42,7 +42,7 @@ static int ralink_deassert_device(struct reset_controller_dev *rcdev,
>   {
>   	u32 val;
>   
> -	if (id < 8)
> +	if (id == 0)
>   		return -1;
>   
>   	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);