Re: [PATCH 02/11] dts: mvebu: Update A8K AP806 SDHCI settings

[Baruch Siach]

Hi Konstantin,

On Wed, Feb 03 2021, kostap@xxxxxxxxxxx wrote:
> From: Konstantin Porotchkin <kostap@xxxxxxxxxxx>
>
> Update the settings for AP806 SDHCI interface according to
> latest Xenon drivers changes.
> - no need to select the PHY slow mode anymore

Why? Has anything changed since the introduction of
marvell,xenon-phy-slow-mode?

baruch

> - recommended to add HS400 support at 1.8V signalling on AP806-B0
> - fix the bus witdth for A8040 DB from 4 to 8 bits.
>
> Signed-off-by: Konstantin Porotchkin <kostap@xxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/marvell/armada-8040-db.dts     | 11 ++++++++++-
>  arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi |  5 -----
>  arch/arm64/boot/dts/marvell/armada-ap80x.dtsi      |  1 -
>  3 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> index 09fb5256f1db..6362e654a823 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> @@ -347,7 +347,16 @@
>  
>  &ap_sdhci0 {
>  	status = "okay";
> -	bus-width = <4>;
> +	bus-width = <8>;
> +	/* The below property should be added to boards with AP806-B0
> +	 * for enabling HS400 speed mode. Otherwise the device highest
> +	 * speed mode will be HS200.
> +	 * Should not be added to boards with earlier release of AP806
> +	 * since it will cause SDHCI driver to fail upon initialization.
> +	 * Reference - HWE-7296210 (errata for releases A0/A1/A2)
> +	 *
> +	 * mmc-hs400-1_8v;
> +	 */
>  	non-removable;
>  };
>  
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> index 73733b4126e2..69653de998e2 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
> @@ -109,11 +109,6 @@
>  
>  &ap_sdhci0 {
>  	bus-width = <8>;
> -	/*
> -	 * Not stable in HS modes - phy needs "more calibration", so add
> -	 * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes.
> -	 */
> -	marvell,xenon-phy-slow-mode;
>  	no-1-8-v;
>  	no-sd;
>  	no-sdio;
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> index 12e477f1aeb9..edd6131a0587 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
> @@ -257,7 +257,6 @@
>  				clock-names = "core";
>  				clocks = <&ap_clk 4>;
>  				dma-coherent;
> -				marvell,xenon-phy-slow-mode;
>  				status = "disabled";
>  			};


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