Re: [PATCH v3 5/5] clk: qcom: Add SDX55 APCS clock controller support

[Stephen Boyd]

Quoting Manivannan Sadhasivam (2021-01-17 20:11:56)
> Add a driver for the SDX55 APCS clock controller. It is part of the APCS
> hardware block, which among other things implements also a combined mux
> and half integer divider functionality. The APCS clock controller has 3
> parent clocks:
> 
> 1. Board XO
> 2. Fixed rate GPLL0
> 3. A7 PLL
> 
> This is required for enabling CPU frequency scaling on SDX55-based
> platforms.
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---

Applied to clk-next