[PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings

From: Steen Hegelund
Date: Wed Feb 10 2021 - 04:29:24 EST


Document the Sparx5 reset device driver bindings

The driver uses two IO ranges on sparx5 for access to
the reset control and the reset status.

Signed-off-by: Steen Hegelund <steen.hegelund@xxxxxxxxxxxxx>
---
.../bindings/reset/microchip,rst.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml

diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index 000000000000..80046172c9f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#";
+$schema: "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@xxxxxxxxxxxxx>
+ - Lars Povlsen <lars.povlsen@xxxxxxxxxxxxx>
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the following
+ functions
+ - One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+ pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,sparx5-switch-reset
+
+ reg:
+ items:
+ - description: cpu block registers
+ - description: global control block registers
+
+ reg-names:
+ items:
+ - const: cpu
+ - const: gcb
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ #reset-cells = <1>;
+ reg = <0x0 0xd0>,
+ <0x11010000 0x10000>;
+ reg-names = "cpu", "gcb";
+ };
+
--
2.30.0