Re: [PATCH v6 02/15] clk: tegra: Don't enable PLLE HW sequencer at init

[Stephen Boyd]

Quoting JC Kuo (2021-01-19 00:55:33)
> PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
> power sequencers' output to enable/disable PLLE. PLLE hardware power
> sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
> are enabled.
> 
> Signed-off-by: JC Kuo <jckuo@xxxxxxxxxx>
> Acked-by: Thierry Reding <treding@xxxxxxxxxx>
> ---

Acked-by: Stephen Boyd <sboyd@xxxxxxxxxx>