Re: [PATCH v3 2/2] drm: bridge: Add TI SN65DSI83/84/85 DSI to LVDS bridge

[kernel test robot]

Hi Jagan,

I love your patch! Perhaps something to improve:

[auto build test WARNING on robh/for-next]
[also build test WARNING on linux/master linus/master v5.11-rc7 next-20210212]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Jagan-Teki/dt-bindings-display-bridge-Add-bindings-for-SN65DSI83-84-85/20210215-014714
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: i386-randconfig-m021-20210215 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@xxxxxxxxx>

New smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:193 sn65dsi_enable() warn: unsigned 'val' is never less than zero.
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:422 sn65dsi_probe() error: uninitialized symbol 'ret'.

Old smatch warnings:
drivers/gpu/drm/bridge/ti-sn65dsi8x.c:214 sn65dsi_enable() warn: unsigned 'val' is never less than zero.

vim +/val +193 drivers/gpu/drm/bridge/ti-sn65dsi8x.c

   170	
   171	static void sn65dsi_enable(struct drm_bridge *bridge)
   172	{
   173		struct sn65dsi *sn = bridge_to_sn65dsi(bridge);
   174		struct drm_display_mode *mode = bridge_to_mode(bridge);
   175		int bpp = mipi_dsi_pixel_format_to_bpp(sn->dsi->format);
   176		unsigned int lanes = sn->dsi->lanes;
   177		unsigned int pixel_clk = mode->clock * 1000;
   178		unsigned int dsi_clk = pixel_clk * bpp / (lanes * 2);
   179		unsigned int val;
   180	
   181		/* reset SOFT_RESET bit */
   182		regmap_write(sn->regmap, SN65DSI_SOFT_RESET, 0x0);
   183	
   184		msleep(10);
   185	
   186		/* reset PLL_EN bit */
   187		regmap_write(sn->regmap, SN65DSI_CLK_PLL, 0x0);
   188	
   189		msleep(10);
   190	
   191		/* setup lvds clock */
   192		val = sn65dsi_get_clk_range(0, 5, pixel_clk, 25000000, 25000000);
 > 193		if (val < 0) {
   194			DRM_DEV_ERROR(sn->dev, "invalid LVDS clock range %d\n", val);
   195			return;
   196		}
   197	
   198		regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK,
   199				   LVDS_CLK_RANGE_MASK, val << LVDS_CLK_RANGE_SHIFT);
   200	
   201		regmap_update_bits(sn->regmap, SN65DSI_LVDS_CLK, HS_CLK_SRC, HS_CLK_SRC);
   202	
   203		/* setup bridge clock divider */
   204		val = (dsi_clk / pixel_clk) - 1;
   205		regmap_update_bits(sn->regmap, SN65DSI_CLK_DIV,
   206				   DSI_CLK_DIV_MASK, val << DSI_CLK_DIV_SHIFT);
   207	
   208		/* configure dsi */
   209		regmap_update_bits(sn->regmap, SN65DSI_DSI_CFG,
   210				   CHA_DSI_LANES_MASK, lanes << CHA_DSI_LANES_SHIFT);
   211	
   212		/* dsi clock range */
   213		val = sn65dsi_get_clk_range(8, 100, dsi_clk, 40000000, 5000000);
   214		if (val < 0) {
   215			DRM_DEV_ERROR(sn->dev, "invalid DSI clock range %d\n", val);
   216			return;
   217		}
   218	
   219		regmap_write(sn->regmap, SN65DSI_DSI_CLK_RANGE, val);
   220	
   221		/* setup lvds modes */
   222		regmap_read(sn->regmap, SN65DSI_LVDS_MODE, &val);
   223		if (mode->flags & DRM_MODE_FLAG_PVSYNC)
   224			val |= VS_NEG_POLARITY;
   225		if (mode->flags & DRM_MODE_FLAG_PHSYNC)
   226			val |= HS_NEG_POLARITY;
   227		if (bpp == 24) /* Channel A mode */
   228			val |= CHA_24BPP_MODE;
   229		regmap_write(sn->regmap, SN65DSI_LVDS_MODE, val);
   230	
   231		/* TODO Channel B is not configure yet */
   232		sn65dsi_configure_cha(sn, mode);
   233	
   234		/* set PLL_EN bit */
   235		regmap_write(sn->regmap, SN65DSI_CLK_PLL, PLL_EN);
   236	
   237		msleep(10);
   238	
   239		/* set SOFT_RESET bit */
   240		regmap_write(sn->regmap, SN65DSI_SOFT_RESET, SOFT_RESET);
   241	
   242		msleep(10);
   243	}
   244	

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0-DAY CI Kernel Test Service, Intel Corporation
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