Re: [Linaro-mm-sig] DMA-buf and uncached system memory

[Christian König]

Am 15.02.21 um 15:41 schrieb David Laight:
> From: Christian König
> > Sent: 15 February 2021 12:05
> ...
> > Snooping the CPU caches introduces some extra latency, so what can
> > happen is that the response to the PCIe read comes to late for the
> > scanout. The result is an underflow and flickering whenever something is
> > in the cache which needs to be flushed first.
> Aren't you going to get the same problem if any other endpoints are
> doing memory reads?

The PCIe device in this case is part of the SoC, so we have a high 
priority channel to memory.

Because of this the hardware designer assumed they have a guaranteed 
memory latency.

> Possibly even ones that don't require a cache snoop and flush.
>
> What about just the cpu doing a real memory transfer?
>
> Or a combination of the two above happening just before your request.
>
> If you don't have a big enough fifo you'll lose.
>
> I did 'fix' a similar(ish) issue with video DMA latency on an embedded
> system based the on SA1100/SA1101 by significantly reducing the clock
> to the VGA panel whenever the cpu was doing 'slow io'.
> (Interleaving an uncached cpu DRAM write between the slow io cycles
> also fixed it.)
> But the video was the only DMA device and that was an embedded system.
> Given the application note about video latency didn't mention what was
> actually happening, I'm not sure how many people actually got it working!

Yeah, I'm also not sure if AMD doesn't solve this with deeper fifos or 
more prefetching in future designs.

But you gave me at least one example where somebody had similar problems.

Thanks for the feedback,
Christian.

> 	David
>
> -
> Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
> Registration No: 1397386 (Wales)
> _______________________________________________
> Linaro-mm-sig mailing list
> Linaro-mm-sig@xxxxxxxxxxxxxxxx
> https://lists.linaro.org/mailman/listinfo/linaro-mm-sig